Alliance MEMORY AS7C34096A Service Manual

August 2004

AS7C34096A

®

3.3V 512K × 8 CMOS SRAM

Features

• Pin compatible to AS7C34096

• Industrial and commercial temperature

• Organization: 524,288 words × 8 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 4/5/6/7 ns output enable access time

• Low power consumption: ACTIVE

- 650 mW / max @ 10 ns

• Low power consumption: STANDBY

- 28.8 mW / max CMOS

Logic block diagram

V

CC

GND

Input buffer

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9

Row decoder

Column decoder

A10

524,288 × 8

Array

(4,194,304)

A11

A12

A13

A14

A15

Sense amp

Control

Circuit

A16

A17

A18

WE
OE
CE

I/O1

I/O8

• Equal access and cycle times

• Easy memory expansion with

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil 36-pin SOJ

- 44-pin TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangements

36-pin SOJ (400 mil)

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A1
A2
A3
A4

CE
I/O1
I/O2

V
GND
I/O3
I/O4

WE

A5
A6
A7
A8
A9

A0
A1
A2
A3
A4

CE
I/O1
I/O2

V

GND
I/O3
I/O4

WE

A5
A6
A7
A8
A9

CC

NC
NC

CC

NC
NC

44-pin TSOP 2

CE, OE

NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND

V

CC

I/O6
I/O5
A14
A13
A12
A11
A10
NC

NC
NC
NC

A18
A17

A16
A15
OE
I/O8
I/O7
GND

V

CC

I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC

inputs

Selection guide

–10 –12 –15 –20 Unit

Maximum address access time 10 12 15 20 ns
Maximum outputenable access time 4 5 6 7 ns

Maximum operating current
Maximum CMOS standby current 8 8 8 8 mA

8/17/04, v. 2.1 Alliance Semiconductor P. 1 of 9

Industrial 180 160 140 110 mA

Commercial 170 150 130 100 mA

Copyright © Alliance Semiconductor. All rights reserved.

AS7C34096A

®

Functional description

The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.

Equal address access and cycle times (t
ideal for high-performance applications. The chip enable input CE
systems.

When CE
CMOS standby mode.

A write cycle is accomplished by asserting write enable (WE
on the rising edge of WE
only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.

is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are

AA

permits easy memory expansion with multiple-bank memory

) and chip enable (CE). Data on the input pins I/O1–I/O8 is written

) or write enable (WE).

) and chip enable (CE), with write enable (WE) high. The chip

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Temperature with V
DC current into output (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func­tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

applied T

CC

t1
t2
D

stg

bias

OUT

–0.5 +5.0 V
–0.5 VCC +0.5 V

–1.0W
–65 +150 °C
–55 +125 °C

–20mA

Truth table

CE WE OE Data Mode

H X X High Z
L H H High Z
LHL

D

OUT

Standby (ISB, I

Output disable (I

Read (ICC)

SB1

CC

)

)

LLX

Key: X = Don’t care, L = Low, H = High

8/17/04, v. 2.1 Alliance Semiconductor P. 2 of 9

D

IN

Write (ICC)

®

Recommended operating condition

Parameter Symbol Min Nominal Max Unit

Supply voltage V
Input voltage

Ambient operating
temperature

*

V

min = –1.0V for pulse width less than 5ns.

IL

**

max = VCC + 2.0V for pulse width less than 5ns.

V

IH

commercial T
industrial T

(10/12/15/20) 3.0 3.3 3.6 V

CC

**

V

IH

*

V

IL

A
A

2.0 – VCC + 0.5 V

–0.5 – 0.8 V

0– 70°C

–40 – 85 °C

DC operating characteristics (over the operating range)1

Parameter Symbol Test conditions

Input leakage

current

Output leakage

current

Operating power

supply current

Standby power

supply current

Output voltage

|I

|I

I

I

V
V

LO

CC

I

SB

SB1

LI

OL
OH

|

|

V

= Max, VIN = GND to V

CC

= Max, CE = V

V

CC

V

= GND to V

OUT

VCC = Max, CE ≤ V

f = f

Max

, I

OUT

= 0mA

VCC = Max, CE ≥ V

CC

IH

CC

IL

Industrial

Commercial

f = f

IH,

Max

VCC = Max,

CE

≥ V

V

≤ 0.2V or VIN ≥ VCC – 0.2V,

IN

CC

– 0.2V,

f = 0

IOL = 8 mA, VCC = Min

IOH = –4 mA, VCC = Min

AS7C34096A

–10 –12 –15 –20

UnitMin Max Min Max Min Max Min Max

–1–1–1–1µA

–1–1–1–1µA

–180–160–140–110mA

- 170 - 150 - 130 - 100 mA
–60–60–60–60mA

–8–8–8–8mA

–0.4–0.4–0.4–0.4 V

2.4–2.4–2.4–2.4– V

Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)

2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C
I/O capacitance C

8/17/04, v. 2.1 Alliance Semiconductor P. 3 of 9

IN

I/O

A, CE, WE, OE

I/O

VIN = 0V 5 pF

= V

V

IN

= 0V 7 pF

OUT