Alliance MEMORY AS7C3256A Service Manual

April 2004

3.3V 32K X 8 CMOS SRAM (Common I/O)

Features

• Pin compatible with AS7C3256

• Industrial and commercial temperature options

• Organization: 32,768 words × 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Very low power consumption: ACTIVE

- 180mW max @ 10 ns

• Very low power consumption: STANDBY

- 7.2 mW max CMOS I/O

• Easy memory expansion with

CE

and OE inputs

AS7C3256A

®

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

- 300 mil SOJ

-8 × 13.4 mm TSOP 1

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

V

CC

GND

Input buffer

A0

A1

A2

A3

A4

A5

A6

A7

Row decoder

256 X 128 X 8

(262,144)

Column decoder

A9A

A10A11A12A13A

8

Array

Sense amp

Control

circuit

14

WE

OE

CE

Pin arrangement

28-pin TSOP 1 (8×13.4 mm)

OE

A11

A9

I/O7

I/O0

A8

A13

WE V

CC

A14 A12

A7 A6 A5 A4 A3 A2

1 2 3 4 5 6 7 8 9 10 11 12 13 14

AS7C3256A

28-pin SOJ (300 mil)

A14 A12

A10

28

CE

27

I/O7

26

I/O6

25

I/O5

24

I/O4

23

I/O3

22 21

GND

20

I/O2

19

I/O1

18

I/O0

17

A0

16

A1

15

I/O0

I/O1 I/O2

GND

1 2 3

A7

4

A6

5

A5

6

A4

7

A3

8

A2 A1 A0

AS7C3256A

9 10 11 12 13 14

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 5 6 7 8 ns

Maximum operating current 50 45 40 35 mA

Maximum CMOS standby current 2 2 2 2 mA

28

V WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3

CC

27 26 25 24 23 22 21 20 19 18 17

16 15

4/23/04; v.2.0 Alliance Semiconductor P. 1 of 9

AS7C3256A

®

Functional description

The AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium permit 3.3V operation without sacrificing performance or operating margins.

The device enters standby mode when power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.

Equal address access and cycle times (t are ideal for high-performance applications. The chip enable ( memory organizations.

A write cycle is accomplished by asserting chip enable ( is written on the rising edge of drive I/O pins only after outputs have been disabled with output enable (

A read cycle is accomplished by asserting chip enable ( chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible. Operation is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged in high volume industry standard packages.

TM

, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques

CE

is high. CMOS standby mode consumes 7.2 mW. Normal operation offers 75%

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns

AA

WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should

CE

) input permits easy memory expansion with multiple-bank

CE

) and write enable (WE) LOW. Data on the input pins I/O0-I/O7

OE

) or write enable (WE).

CE

) and output enable (OE) LOW, with write enable (WE) high. The

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

Ambient temperature with V

DC current into outputs (low) I

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

applied T

CC

t1

t2

D

stg

bias

OUT

–0.5 +5.0 V

–0.5 VCC + 0.5 V

–1.0W

–65 +150

–55 +125

o

C

o

C

–20mA

Truth table

CE WE OE

H X X High Z Standby (I

L H H High Z Output disable (I

LHLD

LLXD

Key: X = Don’t care, L = Low, H = High

OUT

IN

Data Mode

, I

SB

SB1

Read (ICC)

Write (ICC)

CC

)

4/23/04; v.2.0 Alliance Semiconductor P. 2 of 9

®

Recommended operating conditions

Parameter Symbol Min Typical Max Unit

Supply voltage V

Input voltage

Ambient operating temperature

*

V

min = –1.0V for pulse width less than 5ns.

IL

**

max = VCC + 2.0V for pulse width less than 5ns.

V

IH

commercial T

industrial T

CC

**

V

IH

*

V

IL

A

DC operating characteristics (over the operating range)1

-10 -12 -15 -20

Parameter Sym Test conditions

Input leakage current

Output leakage current

Operating power supply current

Standby power supply current

Output voltage

|I

LI

|I

LO

I

CC

I

SB

I

SB1

V

OLIOL

V

OHIOH

= Max,

V

CC

|

V

= GND to V

in

= Max,

V

CC

|

V

= GND to V

OUT

VCC = Max, CE ≤ V f = f

Max

, I

OUT

VCC = Max, CE > V

f = f

Max

CC

IL

= 0mA

IH

–1–1–1–1µA

–50–45–40–35mA

–20–20–20–20mA

VCC = Max, CE > VCC–0.2V V

< 0.2V or

IN

V

> VCC–0.2V, f = 0

IN

–2.0–2.0–2.0–2.0mA

= 8 mA, VCC = Min –0.4–0.4–0.4–0.4V

= –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V

AS7C3256A

3.0 3.3 3.6 V

2.0 – VCC+0.5 V

-0.5 – 0.8 V

0–70oC

–40 – 85

o

UnitMin Max Min Max Min Max Min Max

C

Capacitance (f = 1MHz, T

= room temperature, VCC = NOMINAL)

a

2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

4/23/04; v.2.0 Alliance Semiconductor P. 3 of 9

IN

I/O

A, CE, WE,

OE

I/O Vin = V

Vin = 0V 5 pF

= 0V 7 pF

out

AS7C3256A

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t

Address access time t

Chip enable (CE

Output enable (OE

) access time

Output hold from address change t

CE

LOW to output in low Z

CE

HIGH to output in high Z

OE

LOW to output in low Z

OE

HIGH to output in high Z

Power up time t

Power down time t

RC

AA

t

ACE

t

OE

OH

t

CLZ

t

CHZ

t

OLZ

t

OHZ

PU

PD

Key to switching waveforms

3,9

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

10–12–15–20–ns

– 10 – 12 – 15 – 20 ns 3

–5–6–7–8ns

3–3–3–3–ns5

3–3–3–3–ns4, 5

–3–3–4–5ns4, 5

0–0–0–0–ns4, 5

–3–3–4–5ns4, 5

0–0–0–0–ns4, 5

– 10 – 12 – 15 – 20 ns 4, 5

Undefined output/don’t careFalling inputRising input

Read waveform 1 (address controlled)

Address

t

AA

D

out

Read waveform 2 (CE controlled)

CE

OE

t

CLZ

PU

ACE

D

Supply

current

out

3,6,8,9

t

RC

t

OE

t

OLZ

50% 50%

3,6,7,9

t

RC

1

Data valid

t

OH

t

OHZ

t

CHZ

t

PD

I

CC

I

SB

4/23/04; v.2.0 Alliance Semiconductor P. 4 of 9

AS7C3256A

®

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t

Chip enable to write end t

Address setup to write end t

Address setup time t

Write pulse width t

Write recovery time t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in high Z t

Output active from write end t

Write waveform 1 (WE controlled)

Address

WE

t

AS

D

in

WC

CW

AW

AS

WP

WR

AH

DW

DH

WZ

OW

10,11

t

WZ

11

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

10–12–15–20–ns

8 – 8 –10–12–ns

0–0–0–0–ns

7–8–9–12–ns

0–0–0–0–ns

5–6–8–10–ns

0–0–0–0–ns4, 5

–5–6–7–8ns4, 5

3–3–3–3–ns4, 5

t

WC

t

AW

t

WP

t

DW

Data valid

t

OW

t

AH

WR

DH

D

out

Write waveform 2 (CE controlled)

10,11

t

WC

t

AW

t

AH

Address

t

AS

t

CW

t

WR

CE

t

WP

WE

t

WZ

D

in

D

out

t

DW

Data valid

t

DH

4/23/04; v.2.0 Alliance Semiconductor P. 5 of 9

®

AC test conditions

- Output load: see Figure B

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.3V

320

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

D

out

350

Ω

Figure B: Output load

13

C

GND

Ω

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B. 4 These parameters are specified with CL = 5pF, as i n Figur e s B. Transition is measured 5 This parameter is guaranteed, but not tested.

WE

is High for read cycle.

6 7

CE

and OE are Low for read cycle. 8 Address valid prior to or coincident with 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 N/A 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 N/A 13 C=30pF, except on High Z and Low Z parameters, where C=5pF.

CE

transition Low.

±500mV from steady-state voltage.

Thevenin equivalent

168

D

out

Ω

AS7C3256A

+1.72V

4/23/04; v.2.0 Alliance Semiconductor P. 6 of 9

Package diagrams

AS7C3256A

®

28-pin SOJ

e

Pin 1

28-pin TSOP1

b

E

28-pin SOJ

A

B

b

c D E

e

28-pin TSOP1

A

b

c D

e E

L

α

Min Max

in inches

0.128 0.148

0.026 -

0.095 0.105

0.026 0.032

0.016 0.020

0.007 0.010

0.720 0.730

0.255 0.275

0.295 0.305

0.330 0.340

0.050 BSC

8×13.4 mm

Min Max

1.00 1.20

0.05 0.15

0.91 1.05

0.17 0.27

0.10 0.20

11.70 11.90

0.55 nominal

7.90 8.10

13.20 13.60

0.50 0.70

0° 5°

D

A1

E

A2

E1

E2

B

A

A1

b

c

Seating

Plane

A2

E1 E2

e

c

L

A1AA2

A1

D

Hd

α

A2

Hd

4/23/04; v.2.0 Alliance Semiconductor P. 7 of 9

®

Ordering information

Package / Access time Temperature 10 ns 12 ns 15 ns

Plastic SOJ, 300 mil

TSOP 8x13.4mm

Commercial AS7C3256A-10JC AS7C3256A-12JC AS7C3256A-15JC AS7C3256A-20JC

Industrial AS7C3256A-10JI AS7C3256A-12JI AS7C3256A-15JI AS7C3256A-20JI

Commercial AS7C3256A-10TC AS7C3256A-12TC AS7C3256A-15TC AS7C3256A-20TC

Industrial AS7C3256A-10TI AS7C3256A-12TI AS7C3256A-15TI AS7C3256A-20TI

Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C3256A-10JIN)

Part numbering system

AS7C 3 256A –XX X C or I X

SRAM prefix

Voltage:

3 = 3.3V supply Device number Access time

Packages:

J = SOJ 300 mil T = TSOP 8x13.4mm

Temperature range:

o

C to 70 0C

C = 0

I = -40C to 85C

N= Lead Free Part

AS7C3256A

20 ns

4/23/04; v.2.0 Alliance Semiconductor P. 8 of 9

®

AS7C3256A

®

Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.