Alliance MEMORY AS7C1024B Service Manual

March 2004

Features

• Industrial and commercial temperatures

• Organization: 131,072 words x 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

• Low power consumption: ACTIVE

- 605 mW / max @ 10 ns

• Low power consumption: STANDBY

- 55 mW / max CMOS

• 6T 0.18u CMOS technology

• Easy memory expansion with CE1

• TTL/LVTTL-compatible, three-state I/O

• 32-pin JEDEC standard packages

, CE2, OE inputs

®

5V 128K X 8 CMOS SRAM

- 300 mil SOJ

- 400 mil SOJ

- 8 × 20mm TSOP 1

- 8 x 13.4mm sTSOP 1

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

32-pin SOJ (300 mil) 32-pin SOJ (400 mil)

AS7C1024B

Logic block diagram

V

CC

GND

Input buffer

A0 A1 A2 A3 A4 A5 A6 A7 A8

512 x 256 x 8

(1,048,576)

Row decoder

Column decoder

A9

A10

Array

A11

A12

A13

A14

A15

A16

Sense amp

Control

circuit

I/O7

I/O0

WE OE CE1 CE2

1

NC A16 A14 A12

I/O0 I/O1 I/O2

GND

A11 OE

A9 A8

A13

WE

CE2

A15 V

CC

NC

A16 A14 A12

A7 A6 A5 A4 A3

2 3 4 5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1 A0

32-pin (8 x 20mm) TSOP I

32-pin (8 x 13.4mm) sTSOP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

12 13 14 15 16

AS7C1024B

V

32

CC

A15

31

CE2

30 29

WE

28

A13

27

A8 A9

26

A11

25 24

OE A10

23 22

CE1

21

I/O7 I/O6

20

I/O5

19 18

I/O4

17

I/O3

32

A10

31

CE1

30

I/O7

29 28

I/O6

27

I/O5

26

I/O4

25

I/O3

24

GND

23

I/O2

22

I/O1

21

I/O0

20

A0

19

A1

18

A2

17

Selection guide

-10

-12

Maximum address access time 10 12 15 20 ns

Maximum output enable access time

56 7 8ns

Maximum Operating Current 110 100 90 80 mA

Maximum CMOS standby Current 10 10 10 10 mA

-15 -20 Unit

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AS7C1024B

®

Functional description

The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high performance applications. Active high and low chip enables (CE1

When CE1 static, then full standby power is reached (I conditions.

A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is

). For example, the AS7C1024B is guaranteed not to exceed 55 mW under nominal full standby

SB1

, CE2) permit easy memory expansion with multiple-bank systems.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

Ambient temperature with V

DC current into outputs (low) I

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

applied T

CC

t1

t2

D

stg

bias

OUT

–0.50 +7.0 V

–0.50 VCC +0.50 V

–1.0W

–65 +150 °C

–55 +125 °C

–20mA

Truth table

CE1

H X X X High Z Standby (I

X L X X High Z Standby (I

L H H H High Z Output disable (I

LHHL D

LHLX D

Key: X = don’t care, L = low, H = high

CE2

WE OE

Data Mode

SB

OUT

IN

Read (ICC)

Write (

ICC

, I

SB1

)

CC

)

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Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply Voltage V

Input Voltage

Ambient operating temperature

VIL min = -1.0V for pulse width less than 5ns

VIH max = VCC+2.0V for pulse width less than 5ns.

commercial T

industrial T

AS7C1024B

®

CC

V

IH

V

IL

A

4.5 5.0 5.5 V

2.2 - VCC + 0.5 V

–0.5 – 0.8 V

0–70°C

–40 – 85 °C

DC operating characteristics (over the operating range)

-10 -12 -15 -20

Parameter Sym Test conditions

Input leakage current

Output leakage current

Operating power supply current

Standby power supply current

Output voltage

|I

|VCC = Max, VIN = GND to V

LI

V

= Max, CE1 = VIH or

|

|I

LO

CC

CE2 = V

, V

IL

OUT

VCC = Max, CE1 ≤ VIL,

I

CC

I

SB

CE2 ≥ V

I

OUT

IH

= 0 mA

VCC = Max, CE1 ≥ VIH and/or

CE2 ≤ V

IL

VCC = Max, CE1 ≥ VCC–0.2V

I

V

SB1

OL

OH

and/or CE2 ≤ 0.2V

V

≤ 0.2V or

IN

≥ VCC – 0.2V, f = 0

V

IN

IOL = 8 mA, VCC = Min - 0.4 – 0.4 – 0.4 – 0.4

IOH = –4 mA, VCC = Min 2.4 - 2.4 – 2.4 – 2.4 –

= GND to V

, f = f

Max

,

Min Max Min Max Min Max Min Max

CC

-1–1–1–1µA

CC

- 110 – 100 – 90 – 80 mA

-50–45–45–40

-10–10–10–10

Capacitance (f = 1 MHz, Ta = 25 °C, VCC = NOMINAL)

1

Unit

mA

V

2

Parameter Symbol Signals Te st c ond iti ons Max Unit

Input capacitance C

I/O capacitance C

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IN

I/O

A, CE1, CE2, WE, OE VIN = 0V 5 pF

I/O VIN = V

= 0V 7 pF

OUT

AS7C1024B

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t

Address access time t

Chip enable (CE1

) access time t

Chip enable (CE2) access time t

Output enable (OE

) access time t

Output hold from address change t

CE1

Low to output in low Z t

CE2 High to output in low Z t

CE1

Low to output in high Z t

CE2 Low to output in high Z t

OE

Low to output in low Z t

OE

High to output in high Z t

Power up time t

Power down time t

RC

AA

ACE1

ACE2

OE

OH

CLZ1

CLZ2

CHZ1

CHZ2

OLZ

OHZ

PU

PD

Key to switching waveforms

3,9,12

-10 -12 -15 -20 Unit NotesMin Max Min Max Min Max Min Max

10- 12–15–20–ns

-10–12–15–20ns 3

-10–12–15–20ns3, 12

-5–6–7–8ns

3-3–3–3–ns 5

3 - 3 – 3 – 3 – ns 4, 5, 12

- 4 – 5 – 6 – 7 ns 4, 5, 12

0-0–0–0–ns4, 5

–4–5–6–7ns4, 5

0 - 0 – 0 – 0 – ns 4, 5, 12

–10–12–15–20ns4, 5, 12

Undefined / don’t careFalling inputRising input

OLZ

t

RC1

3,6,7,9,12

t

RC

Data valid

3,6,8,9,12

Data valid

t

OH

t

OHZ

t

, t

CHZ1

CHZ2

t

PD

Read waveform 1 (address controlled)

Address

D

OUT

t

AA

Read waveform 2 (CE1, CE2, and OE controlled)

CE1

CE2

OE

t

D

OUT

Current

supply

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ACE1, tACE2

t

, t

CLZ1

t

PU

CLZ2

t

OE

t

50% 50%

I

CC

I

SB

AS7C1024B

®

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t

Chip enable (CE1

) to write end t

Chip enable (CE2) to write end t

Address setup to write end t

Address setup time t

Write pulse width t

Write recovery time t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in high Z t

Output active from write end t

WC

CW1

CW2

AW

AS

WP

WR

AH

DW

DH

WZ

OW

11, 12

-10 -12 -15 -20 Unit NotesMin Max Min Max Min Max Min Max

10 - 12 – 15 – 20 – ns

8 - 9 – 10 – 12 – ns 12

8 - 9 – 10 – 12 – ns

00–0–0–ns12

78–9–12–ns

0-0 – 0–0– ns

56–8–10–ns

00–0–0–ns4, 5

- 5 – 6 – 7 – 8 ns 4, 5

1 - 1 – 1 – 2 – ns 4, 5

Write waveform 1 (WE controlled)

Address

WE

t

AS

D

IN

D

OUT

10,11,12

t

WZ

t

AW

t

WC

t

WP

t

DW

Data valid

t

OW

t

WR

t

AH

DH

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AS7C1024B

®

Write waveform 2 (CE1 and CE2 controlled)

t

WC

t

AW

Address

t

AS

CW1

, t

CW2

CE1 CE2

t

WP

D

WE

D

OUT

t

WZ

IN

AC test conditions

– Output load: see Figure B.

– Input pulse level: GND to 3.5V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

D

+3.5V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

OUT

255

Figure B: 5V Output load

10,11,12

Ω

t

DW

Data valid

+5V

480

Ω

13

C GND

t t

WR

AH

t

DH

Thevenin equivalent:

168

Ω

D

OUT

+1.728V

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet I 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A and B.

and t

4t

CLZ

5 This parameter is guaranteed, but not 100% tested.

is high for read cycle.

6WE 7CE1

and OE are low and CE2 is high for read cycle. 8 Address valid prior to or coincident with CE1 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 N/A 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 CE1

and CE2 have identical timing. 13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.

are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.

CHZ

transition Low.

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specification.

SB

Package dimensions

AS7C1024B

®

Pin 1

A2

D

e

32-pin SOJ 300

mil

32-pin SOJ 400

mil

Min Max Min Max

E2

E1

A 0.128 0.145 0.132 0.146

A1 0.025 - 0.025 -

B

c

E

A1

b

Seating

Plane

A2 0.095 0.105 0.105 0.115

B 0.026 0.032 0.026 0.032

A

b 0.016 0.020 0.015 0.020

c 0.007 0.010 0.007 0.013

D 0.820 0.830 0.820 0.830

E 0.255 0.275 0.354 0.378

E1 0.295 0.305 0.395 0.405

E2 0.330 0.340 0.435 0.445

e 0.050 BSC 0.050 BSC

b

e

32-pin TSOP 8×20 mm

Min Max

α

A – 1.20

A1 0.05 0.15

c

D

L

Hd

A1AA2

A2 0.95 1.05

b 0.17 0.27

c 0.10 0.21

D 18.30 18.50

pin 1 pin 32

e 0.50 nominal

E 7.90 8.10

Hd 19.80 20.20

L 0.50 0.70

E

pin 16 pin 17

α 0° 5°

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®

Ordering codes

Package \ Access

time

Plastic SOJ, 300 mil

Plastic SOJ, 400 mil

TSOP1 8×20 mm

sTSOP1

8 x 13.4mm

Note: Add suffix ‘N’ to the above part number for LEAD FREE PARTS (Ex: AS7C1024B-10TCN)

Temp

commercial

industrial

commercial

industrial

commercial

-

commercial

industrial

10 ns 12 ns 15 ns 20 ns

AS7C1024B-10TJC AS7C1024B-12TJC AS7C1024B-15TJC AS7C1024B-20TJC

– AS7C1024B-12TJI AS7C1024B-15TJI AS7C1024B-20TJI

AS7C1024B-10JC AS7C1024B-12JC AS7C1024B-15JC AS7C1024B-20JC

– AS7C1024B-12JI AS7C1024B-15JI AS7C1024B-20JI

AS7C1024B-10TC AS7C1024B-12TC AS7C1024B-15TC AS7C1024B-20TC

AS7C1024B-10STC AS7C1024B-12STC AS7C1024B-15STC AS7C1024B-20STC

– AS7C1024B-12STI AS7C1024B-15STI AS7C1024B-20STI

AS7C1024B

Part numbering system

AS7C 1024B –XX X X X

SRAM

prefix

Device

number

Access

time

Package:T = TSOP1 8×20 mm

ST = sTSOP1 8 x 13.4 mm

J = SOJ 400 mil

TJ = SOJ 300 mil

Temperature range

C = Commercial, 0° C to 70° C

I = Industrial, -40° C to 85° C

N = LEAD FREE

PART

3/26/04, v 1.2 Alliance Memory Inc P. 8 of 9

®

Alliance Memory, Inc.

511 Taylor Way,

San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211

Part Number: AS7C1024B

Document Version: v. 1.2

www.alliancememory.com

Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.