Alliance MEMORY AS6C8016 Service Manual

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 1 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

FEATURES

Fast access time : 55ns Low power consumption:

Operating current : 30/20mA (TYP.)

Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7)

UB# (DQ8 ~ DQ15)

Data retention voltage : 2.0V (MIN.)

Lead free and green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

PRODUCT FAMILY

Family

AS6C8016(I)

Operating

Temperature

~ 85℃

-40

Vcc

Range Speed

2.7

~ 5.5V 55ns 6µA(LL) 45/30mA

512K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION

The AS6C8016 is a 8,388,608-bit low power CMOS static random access memory organized as 524,2

88 words by 16 bits. It is fabricated using very

high

performance, high reliability CMOS technology. Its standby current is stable within the range of operating

e AS6C8016 is well designed for low power

Th appl back-up

The AS6C8016 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully

temperature.

ication, and particularly well suited for battery

nonvolatile memory application.

TTL compatible

Power Dissipation Product

Standby(I

SB1,TYP.) Operating(Icc,TYP.)

FUNCTIONAL BLOCK DIAGRAM

Vc

c

Vss

A0-A18

DQ0-DQ7

Lower

DQ

8-DQ15

Upper

CE# WE# OE

LB#

UB#

Byte

#

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

512Kx16

MEMORY

COLUMN I/O

ARRAY

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A18 Address Inputs

DQ0 – DQ15 Data Inputs/Outputs

CE# Chip Enable Input

WE# Write Enable Input

OE# Output Enable Input

LB# Lower Byte Control

UB# Upper Byte Control

VCC Power Supply

VSS Ground

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 2 of 12

AS6C8016

PIN CONFIGURATION

A4

A3

A2

A1

A0

CE #

DQ

DQ 3

Vcc

Vss

DQ

DQ 6

DQ

WE #

A18

A17

A16

A15

A14

1

2

4

5

7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22 23

512K X 16 BIT SUPER LOW POWER CMOS SRAM

A

08C6S 1 6

TS OP II

512K X 8 BIT LOW POWER CMOS SRAM

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

A5

A6

A7

OE

#

UB #

LB

#

DQ

15DQ 0

DQ

14

DQ

13

12

DQ

Vss

Vcc

DQ 11

10

DQ

9

DQ

DQ 8

A8

A9

0

A1

1

A1

2

3

A1

LB#

A

DQ8

B

DQ

C

Vss

D

Vcc

E

DQ14

F

DQ15

G

A18

H

1 2 3 4 5 6

A0

A3

A4UB#

9

DQ10

DQ11

DQ12

DQ1

NC

A8 NC

A6A5

A17

A7

NC

A16

A14

A15

3 DQ5

A13

A12

A10A9 A11

TFBGA

A2OE# A1

CE#

DQ

WE#

NC

0

DQ

2

DQ

1

Vcc

3

Vss

4

DQ

6

DQ7

ABSOLUTE MAXIMUN RATINGS*

PARAMETER SYMBOL RATING UNIT

Voltage on VCC relative to VSS V Voltage on any other pin relative to VSS V Operating Temperature T

Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W

DC Output Current I Soldering Temperature (under 10 sec) T

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specifica

tion is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

T1

-0.5 to 6.5 V

T2

-0.5 to VCC+0.5 V

A

OUT

50 mA

SOLDER

260

-40 to 85(I grade)

℃ ℃

℃

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 3 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

TRUTH TABLE

MODE CE# OE# WE# LB# UB#

Standby

Output Disable

H X

L L L

Read

L L L

Write

L L

Note: H = VIH, L = VIL, X = Don't care.

X X

H H L L L X X X

X

H

L

H

X

H

L

H

L

H

L

X

H

X L

H

L L

H

L L

I/O OPERATION

DQ

0-DQ7 DQ8-DQ15

High High

D

– Z – Z

OUT

High High

High High High – Z

High – Z

D

OUT

D

IN

High – Z

D

IN

D D

OUT

D D

– Z – Z

IN

LY CURRENT

SUPP

I

SB1

ICC,I

I

CC,ICC1

ICC,I

CC1

DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage V Input Low Voltage V Input Leakage Current ILI V Output Leakage

rrent

Cu

TEST CONDITION MIN. TYP.

*1

2.4 - VCC+0.3 V

IH

*2

- 0.2 - 0.6 V

IL

≦≦

CC

V

I

LO

CC

Output Disabled

VIN V V

≦≦

OUT

V

SS

- 1 - 1

Output High Voltage VOH IOH = -1mA 2.4 2.7 - V Output Low Voltage VOL IOL = 2mA - - 0.4 V

Cycle time = Min.

= VIL,

CE#

I

Average Operating

er supply Current

Pow

I

CC1

CC

I

= 0mA

I/O

Other Cycle time = 1µs CE#

Other

pins at VIL or V

≦

0.2V, I

I/O

IH

= 0mA

pins at 0.2V or VCC-0.2V

- 55 -

- - 4 mA

*4

MAX. UNIT

30

60

µ

mA

A

Standby Power Supply

Notes:

1.

2.

3. Over/

4. Typical values are included for reference only and are not guaranteed or tested.

Current

VIH(max) = V

(min) = V

V

IL

Undershoot specifications are characterized, not 100% tested.

Typical valued are measured at V

CAPACITANCE (TA = 25 , f = 1.0MHz)

Input Capacitance C Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

≦

I

+ 3.0V for pulse width less than 10ns.

CC

- 3.0V for pulse width less than 10ns.

SS

CE# VCC-0.2V

SB1

Other

= VCC(TYP.) and TA= 25

CC

pins at 0.2V or VCC-0.2V

℃

- 6 80

℃

PARAMETER SYMBOL MIN. MAX UNIT

6 pF 8 pF

I/O

IN

-

A

µ

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 4 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

AC TEST CONDITIONS

Input Pulse Levels 0.2V to VCC- 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER SYM. UNIT

Read Cycle Time t Address Access Time t Chip Enable Access Time t Output Enable Access Time t Chip Enable to Output in Low-Z t Output Enable to Output in Low-Z t Chip Disable to Output in High-Z t Output Disable to Output in High-Z t Output Hold from Address Change t LB#, UB# Access Time t LB#, UB# to High-Z Output t LB#, UB# to Low-Z Output t

AS6C801

RC

AA

ACE

OE

CLZ

OLZ

CHZ

OHZ

OH

BA

BHZ

BLZ

6

(2) WRITE CYCLE

PARAMETER UNIT

Write Cycle Time t Address Valid to End of Write t Chip Enable to End of Write t Address Set-up Time t Write Pulse Width t Write Recovery Time t Data to Write Time Overlap t Data Hold from End of Write Time t Output Active from End of Write t Write to Output in High-Z t LB#, UB# Valid to End of Write t

*These parameters are guaranteed by device characterization, but not production tested.

SYM.

WC

AW

CW

AS

WP

WR

DW

DH

OW

WHZ

BW

AS6C801

6

Alliance MEMORY AS6C8016 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual