Alliance MEMORY AS6C8016 Service Manual

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 1 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

FEATURES

Fast access time : 55ns Low power consumption:

Operating current : 30/20mA (TYP.)

Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7)

UB# (DQ8 ~ DQ15)

Data retention voltage : 2.0V (MIN.)

Lead free and green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

PRODUCT FAMILY

Family

AS6C8016(I)

Operating

Temperature

~ 85℃

-40

Vcc

Range Speed

2.7

~ 5.5V 55ns 6µA(LL) 45/30mA

512K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION

The AS6C8016 is a 8,388,608-bit low power CMOS static random access memory organized as 524,2

88 words by 16 bits. It is fabricated using very

high

performance, high reliability CMOS technology. Its standby current is stable within the range of operating

e AS6C8016 is well designed for low power

Th appl back-up

The AS6C8016 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully

temperature.

ication, and particularly well suited for battery

nonvolatile memory application.

TTL compatible

Power Dissipation Product

Standby(I

SB1,TYP.) Operating(Icc,TYP.)

FUNCTIONAL BLOCK DIAGRAM

Vc

c

Vss

A0-A18

DQ0-DQ7

Lower

DQ

8-DQ15

Upper

CE# WE# OE

LB#

UB#

Byte

#

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

512Kx16

MEMORY

COLUMN I/O

ARRAY

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A18 Address Inputs

DQ0 – DQ15 Data Inputs/Outputs

CE# Chip Enable Input

WE# Write Enable Input

OE# Output Enable Input

LB# Lower Byte Control

UB# Upper Byte Control

VCC Power Supply

VSS Ground

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 2 of 12

AS6C8016

PIN CONFIGURATION

A4

A3

A2

A1

A0

CE #

DQ

DQ 3

Vcc

Vss

DQ

DQ 6

DQ

WE #

A18

A17

A16

A15

A14

1

2

4

5

7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22 23

512K X 16 BIT SUPER LOW POWER CMOS SRAM

A

08C6S 1 6

TS OP II

512K X 8 BIT LOW POWER CMOS SRAM

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

A5

A6

A7

OE

#

UB #

LB

#

DQ

15DQ 0

DQ

14

DQ

13

12

DQ

Vss

Vcc

DQ 11

10

DQ

9

DQ

DQ 8

A8

A9

0

A1

1

A1

2

3

A1

LB#

A

DQ8

B

DQ

C

Vss

D

Vcc

E

DQ14

F

DQ15

G

A18

H

1 2 3 4 5 6

A0

A3

A4UB#

9

DQ10

DQ11

DQ12

DQ1

NC

A8 NC

A6A5

A17

A7

NC

A16

A14

A15

3 DQ5

A13

A12

A10A9 A11

TFBGA

A2OE# A1

CE#

DQ

WE#

NC

0

DQ

2

DQ

1

Vcc

3

Vss

4

DQ

6

DQ7

ABSOLUTE MAXIMUN RATINGS*

PARAMETER SYMBOL RATING UNIT

Voltage on VCC relative to VSS V Voltage on any other pin relative to VSS V Operating Temperature T

Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W

DC Output Current I Soldering Temperature (under 10 sec) T

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specifica

tion is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

T1

-0.5 to 6.5 V

T2

-0.5 to VCC+0.5 V

A

OUT

50 mA

SOLDER

260

-40 to 85(I grade)

℃ ℃

℃

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 3 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

TRUTH TABLE

MODE CE# OE# WE# LB# UB#

Standby

Output Disable

H X

L L L

Read

L L L

Write

L L

Note: H = VIH, L = VIL, X = Don't care.

X X

H H L L L X X X

X

H

L

H

X

H

L

H

L

H

L

X

H

X L

H

L L

H

L L

I/O OPERATION

DQ

0-DQ7 DQ8-DQ15

High High

D

– Z – Z

OUT

High High

High High High – Z

High – Z

D

OUT

D

IN

High – Z

D

IN

D D

OUT

D D

– Z – Z

IN

LY CURRENT

SUPP

I

SB1

ICC,I

I

CC,ICC1

ICC,I

CC1

DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage V Input Low Voltage V Input Leakage Current ILI V Output Leakage

rrent

Cu

TEST CONDITION MIN. TYP.

*1

2.4 - VCC+0.3 V

IH

*2

- 0.2 - 0.6 V

IL

≦≦

CC

V

I

LO

CC

Output Disabled

VIN V V

≦≦

OUT

V

SS

- 1 - 1

Output High Voltage VOH IOH = -1mA 2.4 2.7 - V Output Low Voltage VOL IOL = 2mA - - 0.4 V

Cycle time = Min.

= VIL,

CE#

I

Average Operating

er supply Current

Pow

I

CC1

CC

I

= 0mA

I/O

Other Cycle time = 1µs CE#

Other

pins at VIL or V

≦

0.2V, I

I/O

IH

= 0mA

pins at 0.2V or VCC-0.2V

- 55 -

- - 4 mA

*4

MAX. UNIT

30

60

µ

mA

A

Standby Power Supply

Notes:

1.

2.

3. Over/

4. Typical values are included for reference only and are not guaranteed or tested.

Current

VIH(max) = V

(min) = V

V

IL

Undershoot specifications are characterized, not 100% tested.

Typical valued are measured at V

CAPACITANCE (TA = 25 , f = 1.0MHz)

Input Capacitance C Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

≦

I

+ 3.0V for pulse width less than 10ns.

CC

- 3.0V for pulse width less than 10ns.

SS

CE# VCC-0.2V

SB1

Other

= VCC(TYP.) and TA= 25

CC

pins at 0.2V or VCC-0.2V

℃

- 6 80

℃

PARAMETER SYMBOL MIN. MAX UNIT

6 pF 8 pF

I/O

IN

-

A

µ

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 4 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

AC TEST CONDITIONS

Input Pulse Levels 0.2V to VCC- 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER SYM. UNIT

Read Cycle Time t Address Access Time t Chip Enable Access Time t Output Enable Access Time t Chip Enable to Output in Low-Z t Output Enable to Output in Low-Z t Chip Disable to Output in High-Z t Output Disable to Output in High-Z t Output Hold from Address Change t LB#, UB# Access Time t LB#, UB# to High-Z Output t LB#, UB# to Low-Z Output t

AS6C801

RC

AA

ACE

OE

CLZ

OLZ

CHZ

OHZ

OH

BA

BHZ

BLZ

6

(2) WRITE CYCLE

PARAMETER UNIT

Write Cycle Time t Address Valid to End of Write t Chip Enable to End of Write t Address Set-up Time t Write Pulse Width t Write Recovery Time t Data to Write Time Overlap t Data Hold from End of Write Time t Output Active from End of Write t Write to Output in High-Z t LB#, UB# Valid to End of Write t

*These parameters are guaranteed by device characterization, but not production tested.

SYM.

WC

AW

CW

AS

WP

WR

DW

DH

OW

WHZ

BW

AS6C801

6

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 5 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

Address

CE#

Previous Data Valid

tRC

tAA

tACE

tOHtAA

LB#,UB#

tBA

OE#

tOE

tOLZ

tBLZ

tCLZ

Dout Data Valid

Notes :

1.WE#is high for read

2.Device is continuous

3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.

4.t

, t

CLZ

BLZ, tOLZ

ny given temperature and voltage condition, t

5.At a

cycle.

ly selected OE# = low, CE# = low, LB# or UB# = low

, t

CHZ,tBHZ

and t

are specified with CL= 5pF. Transition is measured ±500mV from steady state.

OHZ

is less than t

CHZ

CLZ

, t

.

BHZ

is less than t

tOH

tBHZ tCHZ

tOHZ

BLZ

, t

is less than t

OHZ

High-ZHigh-Z

OLZ.

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 6 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

tWC

Address

tAW

CE#

tCW

tBW

LB#,UB#

tWP

WE#

tWHZ

Dout

n Data Valid

Di

(4)

High-Z

tDW tDH

tWRtAS

TOW

(4)

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

tWC

Address

tAW

CE#

tCW

tBW

LB#,UB#

tWP

WE#

tWHZ

Dout

Din Data Valid

(4)

High-Z

tDW tDH

tWRtAS

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 7 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

WRITE CYCLE 3

Address

CE#

LB#,UB#

WE#

Dout

n Data Valid

Di

(LB#

,UB#

Controlled)

tAS

(4)

(1,2,5,6)

tAW

tWHZ

512K X 8 BIT LOW POWER CMOS SRAM

tWC

tCW

tBW

tWP

tWR

High-Z

tDW tDH

Notes :

1.WE#,CE#, LB A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

2.

3.During a WE#

placed on the b

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB

state.

and t

6.t

OW

#, UB# must be high during all address transitions.

controlled write c

us.

#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

WHZ

ycle with OE# low, tWP must be greater than t

+ tDW to allow the drivers to turn off and data to be

WHZ

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 8 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

VCC for Data Retention VDR CE# VCC- 0.2V 2.0 - 5.5 V

>_

VCC= 2.0V

Data Retention Current I

Chip Disable to Data Retenti

on Time

t

CDR

DR

>_

VCC-0.2V

CE#

pins at 0.2V or VCC-0.2V

Other See Data Retention

Waveforms (below) Recovery Time tR t t

= Read Cycle Time

RC

*

-I - 5 50

0 - - ns

- - ns

RC

*

µ

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1)

Vcc

CE#

Vcc(min.)

VIH

(CE# controlled)

>_

VDR 2.0V

>_

CE#

Vcc-0.2V

Vcc(min.)

tRtCDR

VIH

A

Low Vcc Data Retention Waveform (2)

Vcc

LB#,UB#

Vcc(min

.)

VIH

(LB#, UB# controlled)

>_

VDR 2.0V

LB#,UB# Vcc-0.2V

>_

Vcc(min.)

tRtCDR

VIH

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 9 of 12

A S 6 C 8 0 1 6

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

44-pin 400mil TSOP-ⅡⅡ Package Outline Dimension

θ

SYMBOLS

A - - 1.20 - - 47.2 A1 0.05 0.10 0.15 2.0 3.9 5.9 A2 0.95 1.00 1.05 37.4 39.4 41.3

b 0.30 - 0.45 11.8 - 17.7

c 0.12 - 0.21 4.7 - 8.3 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473

E1 9.957 10.160 10.363 392 400 408

e - 0.800 - - 31.5 L 0.40 0.50 0.60 15.7 19.7 23.6

ZD - 0.805 - - 31.7 -

y - - 0.076 - - 3

Θ

0

DIMENSIONS IN MILLMETERS DIMENSIONS IN MILS

MIN.

NOM. MAX. MIN. NOM. MAX.

o

3o 6o 0o 3o 6

o

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 10 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

48-ball 6mm × 8mm TFBGA Package Outline Dimension

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 11 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

Alliance Organization

AS6C8016 -55ZIN 512K x 16 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 F - 85 F 55

AS6C8016 -55BIN 512K x 16 2.7 - 5.5V 48ball TBGA Industrial ~ -40 F - 85 F 55

VCC

Range

Package Operating Temp

PART NUMBERING SYSTEM

AS6C 8016 -55 X X N

low power SRAM prefix

Device Number Package Option Temperature Range

380 = 8M Z - 44pin TSOP I = Industrial

= x16

16

Access

e

Tim

B = 48ball TFBGA

(-40 to + 85 C)

N = Lead Free RoH

S

compliant

Speed

ns

part

January 2007

512K X 16 BIT LOW POWER CMOS SRAM

NOVEMBER 2007

AS6C8016

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 12 of 12

512K X 8 BIT LOW POWER CMOS SRAM

®

Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211

www.alliancememory.com

© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inAlliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofAlliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use.

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