Alliance MEMORY AS6C8008 Service Manual

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 1 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

FEATURES

Fast access time : 55ns Low power consumption:

Operating current : 30/20mA (TYP.)

Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.)

Lead free and green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

PRODUCT FAMILY

Product

Family

AS6C8008(I)

Operating

Temperature

~ 85℃

-40

Range Speed

Vcc

2.7

~ 5.5V 55ns 6µA(LL) 30/20mA

512K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION

The AS6C8008 is a 8,388,608-bit low power CMOS static random access memory organized as 1,048,5 high Its standby current is stable within the range of operating

The AS6C8008 power suited appl

The AS6C8008 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully

76 words by 8 bits. It is fabricated using very

performance, high reliability CMOS technology.

temperature.

is well designed for very low system applications, and particularly well for battery back-up nonvolatile memory

ication.

TTL compatible

Power Dissipation

Standby(I

SB1,TYP.) Operating(Icc,TYP.)

FUNCTIONAL BLOCK DIAGRAM

Vc

c

Vs

s

A0-A19

DQ0-DQ

CE# CE2

WE

# #

OE

DECODER

7

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

1024Kx8

MEMORY

COLUMN I/O

ARRAY

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A19 Address Inputs

DQ0 – DQ7 Data Inputs/Outputs

CE#, CE2 Chip Enable Inputs

WE# Write Enable Input

OE# Output Enable Input

VCC Power Supply

VSS Ground

NC No Connection

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 2 of 11

AS6C8008

PIN CONFIGURATION

A4

A3

A2

A1

A0

CE #

NC

DQ

DQ 1

Vcc

Vss

DQ

NC

WE #

A19

A18

A17

A16

A15

0

2

3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22 23

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

A

C6S 08

0 8

TS OP -II

512K X 8 BIT LOW POWER CMOS SRAM

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

A5

A6

A7

OE

CE 2

A8

NCNC

NC

DQ

Vss

Vcc

DQ

NC

A9

A1

#

7

6

5

4

0

1

2

3

4

A

B

DQ

C

D

E

DQ

F

G

H

NC

Vss

Vcc

NC

A18

1 2 3 4 5 6

A0

A3

A4NC

NC

0

DQ

NC NC

3

A8 A19

1

2

A17 A7

NC

A16

A14

A15

A12

A13

A10A9 A11

TFBGA

A6A5

A2OE# A1

CE

NC

DQ5

DQ6

WE

#

CE2

NC

DQ

Vcc

Vss

DQ7

NCNC

4

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 3 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

Voltage on VCC relative to VSS VT1 -0.5 to 6.5 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V

Operating Temperature TA

-40 to 85(I grade)

Storage Temperature TSTG -65 to 150

℃ ℃

Power Dissipation PD 1 W DC Output Current IOUT 50 mA Soldering Temperature (under 10 sec) TSOLDER 260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

ting only and functional operation of the device or any other conditions above those indicated in the operational sections of this

ra specifica

tion is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

℃

TRUTH TABLE

MODE

Standby

CE#

H X X X

X L X X Output Disable

Read

Write

Note: H = VIH, L = VIL, X = Don't care.

L H H H

L H L H

L H X L

CE2 OE# WE#

OPERATION

I/O

Hig

h-Z I

Hig

h-Z I

h-Z ICC,I

Hig

D

OUT

DIN ICC,I

ICC,I

SUPP

LY CURRENT

SB1

CC1

DC ELECTRICAL CHARACTERISTICS

PARAMETER

Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage V Input Low Voltage V Input Leakage Current ILI V Output Leakage

rrent

Cu

SYMBOL TEST CONDITION MIN. TYP.

*1

2.4 - VCC+0.3 V

IH

*2

- 0.2 - 0.6 V

IL

≧

CC

V

I

LO

CC

Output Disabled

VIN V

≧

V

OUT

≧

V

SS

- 1 - 1

Output High Voltage VOH IOH = -1mA 2.4 2.7 - V Output Low Voltage VOL IOL = 2mA - - 0.4 V

Cycle time = Min.

= V

Average Operating

er supply Current

Pow

Standby Power Supply

Current

I

CC1

I

SB1

CE#

CC

I

= 0mA

I/O

Other Cycle time = 1µs CE# I

= 0mA

I/O

Other CE# VCC-0.2V or CE2

Other

and CE2 = V

IL

pins at VIL or V

≦

0.2V and CE2

IH

≧

VCC-0.2V

pins at 0.2V or VCC-0.2V

≧

≦

2V

0.

pins at 0.2V or VCC-0.2V

- 55 -

- - 4 mA

- 6 80

*4

MAX. UNIT

30 60

µ

mA

µ

A

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 4 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

Notes:

1.

VIH(max) = V

(min) = V

V

2.

IL

Undershoot specifications are characterized, not 100% tested.

3. Over/

4. Typical values are included for reference only and are not guaranteed or tested.

Typical valued are measured at V

CAPACITANCE (TA = 25 , f = 1.0MHz)

+ 3.0V for pulse width less than 10ns.

CC

- 3.0V for pulse width less than 10ns.

SS

= VCC(TYP.) and TA= 25

CC

?

512K X 8 BIT LOW POWER CMOS SRAM

℃

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

I/O

IN

-

6 pF 8 pF

AC TEST CONDITIONS

Input Pulse Levels 0.2V to VCC- 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER

Read Cycle Time t Address Access Time t Chip Enable Access Time t Output Enable Access Time t Chip Enable to Output in Low-Z t Output Enable to Output in Low-Z t Chip Disable to Output in High-Z t Output Disable to Output in High-Z t Output Hold from Address Change t

SYM

RC

AA

ACE

OE

CLZ

OLZ

CHZ

OHZ

OH

.

AS6C800

8

(2) WRITE CYCLE

PARAMETER

Write Cycle Time t Address Valid to End of Write t Chip Enable to End of Write t Address Set-up Time t Write Pulse Width t Write Recovery Time t Data to Write Time Overlap t Data Hold from End of Write Time t Output Active from End of Write t Write to Output in High-Z t

*These parameters are guaranteed by device characterization, but not production tested.

SYM

WC

AW

CW

AS

WP

WR

DW

DH

OW

WHZ

.

AS6C800

8

UNIT

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 5 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout Data Valid

READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)

Address

CE#

Previous Data Valid

tRC

tAA

tACE

tOHtAA

CE2

OE#

tOE

tOLZ

tCLZ

Dout Data Valid

Notes :

1.WE# is high for read

2.Device is continuous

3.Address must be valid prior to or coincident with CE# = low,CE2 = high; otherwise tAA is the limiting parameter.

4.t

, t

CLZ

OLZ

CHZ

5.At a

ny given temperature and voltage condition, t

cycle.

ly selected OE# = low, CE# = low

and t

are specified with CL= 5pF. Transition is measured ±500mV from steady state.

OHZ

CE2 = high

.,

is less than t

CHZ

.

CLZ

, t

OHZ

is less than t

tOH

tOHZ

tCHZ

High-ZHigh-Z

OLZ.

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 6 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

tWC

Address

tAW

CE#

tCW

CE2

tWP

WE#

tWHZ

Dout

Din Data Valid

(4)

High-Z

tDW tDH

tWRtAS

TOW

(4)

WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)

tWC

Address

tAW

CE# tWRtAS

tCW

CE2

tWP

WE#

tWHZ

Dout

Di

n Data Valid

Notes :

1.WE#, CE

2.

A write occurs during the overlap of a low CE#, high CE2, low WE#.

3.During a WE#

placed on the b

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#l

impedance s

6.t

OW

# must be high or CE2 must be low during all address transitions.

controlled write cycle with OE# low, tWP must be greater than t

us.

ow transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high

and t

tate. are specified with CL = 5pF. Transition is measured ±500mV from steady state.

WHZ

(4)

High-Z

tDW tDH

+ tDW to allow the drivers to turn off and data to be

WHZ

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 7 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

VCC for Data Retention VDR CE# VCC- 0.2V or CE2 0.2V 2.0 - 5.5 V

>_

VCC= 2.0V

Data Retention Current I

Chip Disable to Data Retention Time

Recovery Time t t

= Read Cycle Time

RC

*

t

CDR

DR

>_

CE#

V

pins at 0.2V or VCC- 0.2V

Other

See Data Retention Waveforms (below)

R

- 0.2V or CE2 0.2V

CC

>_

-I

- 5 50

0 - - ns

t

- - ns

RC

*

µ

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE#

Vcc

CE#

Vcc(min

.)

VIH

controlled)

>_

VDR 2.0V

>_

CE#

Vcc-0.2V

Vcc(min.)

tRtCDR

VIH

A

Low Vcc Data Retention Waveform (2)

Vcc(m

Vcc

CE2

in.)

VIL

(CE2 controlled)

>_

VDR 2.0V

>_

CE2 0.

Vcc(min.)

tRtCDR

2V

VIL

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 8 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

44-pin 400mil TSOP-II Package Outline Dimension

θ

SYMBOLS

A - - 1.20 - - 47.2 A1 0.05 0.10 0.15 2.0 3.9 5.9 A2 0.95 1.00 1.05 37.4 39.4 41.3

b 0.30 - 0.45 11.8 - 17.7

c 0.12 - 0.21 4.7 - 8.3 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473

E1 9.957 10.160 10.363 392 400 408

e - 0.800 - - 31.5 L 0.40 0.50 0.60 15.7 19.7 23.6

ZD - 0.805 - - 31.7 -

y - - 0.076 - - 3

Θ

0

DIMENSIONS IN MILLMETERS DIMENSIONS IN MILS

NOM. MAX. MIN. NOM. MAX.

MIN.

o

3o 6o 0o 3o 6

o

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 9 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

48-ball 6mm × 8mm TFBGA Package Outline Dimension

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

1024K X 8 BIT LOW POWER CMOS SRAM

JANUARY 2008

AS6C8008

JANUAR/2008, V 1.0

Alliance Memory Inc.

Page 10 of 11

ORDERING INFORMATION

512K X 8 BIT LOW POWER CMOS SRAM

Alliance Organization VCC Range Package Operating Temp

AS6C8008-55ZIN 1024K x 8 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 F - 85 F 55

AS6C8008-55BIN 1024K x 8 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 F - 85 F 55

PART NUMBERING SYSTEM

AS6C 8008 -55 X X N

low power S RAM prefix

Device Number Package Option Temperature Range

380 =8M Z - 44pin TSOP I = Industrial

08

= x8

Access Tim

e

B = 48ball TFBGA

(-40 to + 85 C)

N = Lead Free

S

RoH compliant

Speed

ns

part

January 2007

1024K X 8 BIT LOW POWER CMOS SRAM

JANUARY 2008

AS6C8008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 11 of 11

512K X 8 BIT LOW POWER CMOS SRAM

®

Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211

www.alliancememory.com

© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inAlliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofAlliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use.

Rights Reserved

All