Alliance MEMORY AS6C4008 Service Manual

January 2007

512K X 8 BIT LOW POWER CMOS SRAM

OCTOBER 2007

AS6C4008

10/OCTOBER/07, V.1.1

Alliance Memory Inc.

Page 1 of 1

512K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Coming
Soon!

Access time : 55 ns

Low power consumption:
Operatingcurrent : 30/20mA (TYP.)
Standby current : 4µA (TYP.) C-version

Single 2.7V ~ 5.5V power supply

Fully Compatible with all Competitors 5V product

Fully Compatible with all Competitors 3.3V product

Fully static operation

Tri-state output

Data retention voltage : 2.0V (MIN.)

All products ROHS Compliant

Package:32-pin 450 mil SOP

32-pin 8mm x 20mm TSOP-I

32-pin 600 mil P-DIP

:

32-pin 8mm x 13.4mm sTSOP

*36-ball 6mm x 8mm TFBGA
*

GENERAL DESCRIPTION

The AS6C4008 is a 4,194,304-bit low power
CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.

The AS6C4008 is well designed for very low power
system applications, and particularly well suited for
battery back-up non -volatile memory application.

T he AS6C4008 operates from a single power
supply of 2.7V ~ 5.5V

.

FUNCTIONAL BLOCK DIAGRAM

Vcc
Vss

A0-A18

DQ0-DQ7

CE#
WE#
OE#

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

512Kx8

MEMORY ARRAY

COLUMN I/O

PIN DESCRIPTION**

SYMBOL DESCRIPTION

A0 - A18 Address Inputs

DQ0 – DQ7 Data Inputs/Outputs

CE# Chip Enable Inputs

WE# Write Enable Input

OE# Output Enable Input

V

CC

V

SS

NC No Connection

Power Supply

Ground

PIN CONFIGURATION

512K X 8 BIT LOW POWER CMOS SRAM

OCTOBER 2007

AS6C4008

10/OCTOBER/07, V.1.1

Alliance Memory Inc.

Page 2 of 15

®

A18

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

Vss

A8

DQ0

DQ1

Vcc

Vss

DQ2

DQ3

Vcc

A15

A17

WE#

A13

A8

A9

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

A11

A9
A8

A13

WE#

A17
A15
Vcc
A18
A16
A14
A12

A7
A6
A5
A4 A3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

AS6C4008

TSOP-I/sTSOP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1716

OE#

A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

Vss
DQ2
DQ1
DQ0

A0
A1
A2

A6A1 A3

A7

A4A2

A5NC

A17

A15

A16

A12A11 A13

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

1716

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A0

A

DQ4

B

DQ5

C

Vss

D

Vcc

E

DQ6

F

DQ7

G

A9

H

AS6C4008

SOP/P-DIP

NC

WE#

A18

OE#

CE#

A10 A14

1 2 3 4 5 6

TFBGA

®

512K X 8 BIT LOW POWER CMOS SRAM

OCTOBER 2007

AS6C4008

10/OCTOBER/07, V.1.1

Alliance Memory Inc.

Page 3 of 15

ABSOLUTE MAXIMUM RATINGS*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS VTERM -0.5 to 6.5 V

0 to 70(C grade)

TerutarepmeTgnitarepO A

ºC

-40 to 85(I grade)

TerutarepmeTegarotS STG -65 to 150 ºC

PnoitapissiDrewoP D 1 W

ItnerruCtuptuOCD OUT 50 mA

Soldering Temperature (under 10 sec) TSOLDER 260 ºC

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

Standby
Output Disable
Read
Write

Note: H = VIH, L = VIL, X = Don't care.

CE# OE# WE#

H X X High-Z I
L H H High-Z I
L L H D
L X L D

I/O OPERATION

OUT

IN

SUPPLY CURRENT

DC ELECTRICAL CHARACTERISTICS

PARAMETER

Supply Voltage V
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
Output Leakage
Current
Output High Voltage V
Output Low Voltage V

Average Operating
Power supply Current

SYMBOL TEST CONDITION MIN. TYP.

CC

*1

IH

*1

IL

VCC≧ VIN≧ V

LI

VCC≧ V

I

LO

Output Disabled

OHIOH

OLIOL

Cycle time = Min.

I

CC

CE# = 0.2V, I

SS

≧ VSS,

OUT

= 2mA - - 0.4 V

- 55 -

= 0mA

I/O

V*7.0

CC

- 1 - 1

- 1 - 1

other pins at 0.2V or VCC- 0.2V

Cycle time = 1µs

I

CC1

CE# = 0.2V, I

I/O

= 0mA

-

other pins at 0.2V or VCC- 0.2V

Standby Power
Supply Current

Notes: 1. VIH(max) = VCC+ 3.0V for pulse width less than 10ns. VIL(min) = VSS- 3.0V for pulse width less than 10ns.

2. Over/Undershoot specifications are characterized, not 100% tested.

3. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC= VCC(TYP.) and TA= 25ºC

4. 25µA for special request

*C=Commercial temperature/I = Industrial temperature

I

SB1

CE# V≧CC- 0.2V

*C 4 50
*I

-

-

*3

MAX. UNIT

- VCC+0.3 V

30 60

4

4 50

SB1

CC,ICC1

ICC,I

CC1

ICC,I

CC1

10 mA

*4

*4

V5.50.37.2

V6.0-2.0-

µ

µ

V--4.2Am1-=

mA

µ
µ

A

A

A
A

®

512K X 8 BIT LOW POWER CMOS SRAM

OCTOBER 2007

AS6C4008

10/OCTOBER/07, V.1.1

Alliance Memory Inc.

Page 4 of 15

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Address

tAW

CE#

WE#

tWHZ

Dout

Din

(4)

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

tCW

tWP

tWC

High-Z

tDW tDH

Data Valid

tWRtAS

TOW

(4)

tWC

Address

tAW

CE# tWRtAS

tCW

tWP

WE#

tWHZ

Dout

Din

Notes :

1.WE#, CE# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#.

3.During a WE# controlled write cycle with OE# low, t
placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.

6.t

OW

and t

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

WHZ

(4)

must be greater than t

WP

High-Z

tDW tDH

Data Valid

+ tDW to allow the drivers to turn off and data to be

WHZ

AS6C4008

10 October 2007, v 1.1

Alliance Memory Inc.,

OCTOBER 2007

Rev. 1.1

Notes:

1. V

2. V

3. Over/Undershoot specifications are characterized, not 100% tested.

4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V

(max) = V

IH

(min) = V

IL

+ 3.0V for pulse width less than 10ns.

CC

- 3.0V for pulse width less than 10ns.

SS

512K X 8 BIT LOW POWER CMOS SRAM

= VCC(TYP.) and TA= 25

CC

?

CAPACITANCE (TA = 25 , f℃ = 1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

C ecnaticapaC tupnI

IN

Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

I/O

-

-

AC TEST CONDITIONS

V ot V2.0 sleveL esluP tupnI

- 0.2V

CC

sn3 semiT llaF dna esiR tupnI

Input and Output Timing Reference Levels 1.5V

C daoL tuptuO

= 30pF + 1TTL, IOH/IOL = -1mA/2mA

L

AC ELECTRICAL CHARACTERISTICS

6 pF
8 pF

(1) READ CYCLE

PARAMETER SYM.

AS6C4008-55

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time tRC 55 - ns
Address Access Time tAA - 55 ns
Chip Enable Access Time t

- 55 ns

ACE

Output Enable Access Time tOE - 30 ns
Chip Enable to Output in Low-Z t
Output Enable to Output in Low-Z t
Chip Disable to Output in High-Z t
Output Disable to Output in High-Z t

* 10 - ns

CLZ

* 5 - ns

OLZ

* - 20 ns

CHZ

* - 20 ns

OHZ

Output Hold from Address Change tOH 10 - ns

(2) WRITE CYCLE

PARAMETER SYM.

AS6C4008-55

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time tWC 55 - ns
Address Valid to End of Write tAW 50 - ns
Chip Enable to End of Write tCW 50 - ns
Address Set-up Time tAS 0 - ns
Write Pulse Width tWP 45 - ns
Write Recovery Time tWR 0 - ns
Data to Write Time Overlap tDW 25 - ns
Data Hold from End of Write Time tDH 0 - ns
Output Active from End of Write tOW* 5 - ns
Write to Output in High-Z t

*These parameters are guaranteed by device characterization, but not production tested.

* - 20 ns

WHZ

Page 5 of 15