ALLIANCE AS6C4008-55SIN Datasheet

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

SYMBOL

DESCRIPTION

A0 - A18

Address Inputs

DQ0 – DQ7

Data Inputs/Outputs

CE#

Chip Enable Inputs

WE#

Write Enable Input

OE#

Output Enable Input

V

Power Supply

V

Ground

NC

No Connection

FEATURES GENERAL DESCRIPTION

Product

Family

Operating

Temperature

Power Dissipation

Standby(ISB1TYP.)

Operating(Icc,TYP.)

AS6C4008

-40 ~ +85

2.7 ~ 5.5V

55ns

4µA(LL)

30mA

Access time : 55 ns

Low power consumption: Operating current : 30 mA (TYP.) Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible

Fully static operation

Tri-state output

Data retention voltage :1.5V (MIN.)

All products ROHS Compliant

Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP

32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 36-ball 6mm x 8mm TFBGA 32-pin 400 mil TSOP-II

PRODUCT FAMILY

Vcc Range Speed

℃

The AS6C4008 is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.

The AS6C4008 is well designed for very low power system applications, and particularly well suited for battery back-up non-volatile memory application.

The AS6C400

8 op erates from a sing le p owe r sup p ly of 2.7V~ 5.5Vand all inputs and outputs are fully TTL compatible

FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION**

Vcc Vss

512Kx8

A0-A18

DQ0-DQ7

CE# WE# OE#

DECODER

CONTROL

I/O DATA CIRCUIT

CIRCUIT

MEMORY ARRAY

COLUMN I/O

CC SS

AUG/09, v 1.4 Alliance Memory Inc

Page 1 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

1

32

2

31 3 30 4 29

5

28 6 27 7 26

8

25

10

AS6C4008

23

11

22

21

13

20

14

19

15

18

16

17

1

32

2

31

5

28

6

27 7 26

8

25

AS6C4008

9

24

PIN CONFIGURATION

A18 1 32 Vcc A16 2 A14 3 A12 4

A7 5 28 A13 A6 6 A5 7 A4 A3 9 A2 10 A1 11

A0 12 DQ0 13 DQ1 14 DQ2 15

Vss 16

8

AS6C4008

SOP/ P-DIP

31 A15 30 A17 29 WE#

27 A8 26 A9 25 A11 24 OE# 23 A10 22 21 DQ7 20 DQ6 19 18 DQ4 17 DQ3

CE#

DQ5

A11

A9 A8

A13

WE#

A17 A15

Vcc A18 9 A16 A14 A12 12

A7 A6 A5 A4 A3

TSOP-I/STSOP

24 Vss

OE#

A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

DQ2 DQ1 DQ0

A0 A1 A2

A18

A16

A14 A17

A12

A7 A1 3

A6 A8

A5 A9

A4 A1 1

A3

A2

A1

A0

DQ0

DQ1

DQ2 DQ4

VSS DQ3

3 30

4

10 23

11 22

12 21

13 20

14 19

15 18

16 17

TSOP -II

29

VCC

A15

W E#

OE #

A10

CE #

DQ7

DQ6

DQ5

A0

A B C D E F

G H

A1 NC

DQ4

A2 WE#

DQ5

NC

Vss

Vcc

DQ6

A18

DQ7 OE#

A 9

1 2 3 4 5 6

CE# A16 A15

A10 A11 A12 A13

TFBGA

A3

A6 A8

A4

A7 DQ0

A5

DQ1

Vcc

Vss

DQ2

A17

DQ3

A14

AUG/09, v 1.4 Alliance Memory Inc

Page 2 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

PARAMETER

SYMBOL

RATING

UNIT

Terminal Voltage with Respect to VSS

VTERM

-0.5 to 6.5

V

Storage Temperature

TSTG

-65 to 150

C

Power Dissipation

PD1

W

DC Output Current

I

50

mA

Soldering Temperature (under 10 sec)

T

260

C

MODE

CE#

OE#

WE#

I/O OPERATION

SUPPLY CURRENT

Standby

H X X

High-Z

I

Output Disable

L H H

High-Z

ICC,I

Read

L L H

D

ICC,I

Write

L X L

DINICC,I

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

*3

MAX.

UNIT

Supply Voltage

V

CC

2.7

3.0

5.5

V

Input High Voltage

Vcc: 4.5 ~ 5.5V

VCC+0.3

Vcc: 2.7 ~ 4.5V

Input Low Voltage

Vcc: 4.5 ~ 5.5V

- 0.2 - 0.8

V

Vcc: 2.7 ~ 4.5V

- 0.2 - 0.6

V

Input Leakage Current

I

V

- 1 - 1

µ

A

Output Leakage Current

V

VSS,

Output Disabled

Output High Voltage

V

OH

I

OH

= -1mA

2.4 - -

V

Output Low Voltage

V

OL

I

OL

= 2mA

- - 0.4

V

Cycle time = Min. CE# other pins at 0.2V or V

CC

- 0.2V

Cycle time = 1µs

other pins at 0.2V or V

CC

- 0.2V

Standby Power

-LL - 4

*4

µ

A

-LLE/-LLI

-

4

µ

A

ABSOLUTE MAXIMUM RATINGS*

0 to 70(C grade)

Operating Temperature TA

C

o

-40 to 85(I grade)

o

OUT

SOLDER

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating on specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

ly and functional operation of the device or any other conditions above those indicated in the operational sections of this

o

TRUTH TABLE

Note: H = VIH, L = VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

*1

VIH

*1

VIL

≧ ≧

IN OUT

≧

Average Operating Power supply Current

I

LO

I

CC

I

CC1

LI

CE# = 0.2V, I

CC CC

= 0.2V, I

≧

I/O

SS

= 0mA

SB1

CC1

OUT

2.4 -

2.2 -

- 1 - 1

- 55 -

- 4 10

30 60

VCC+0.3

CC1 CC1

V V

A

µ

mA

SB1

CE# ≧V

Supply Current

Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. VIL(min) = VSS - 3.0V for pulse width less than 10ns.

2.

Over/Undershoot specifications are characterized, not 100% tested.

3.

Typical values are included for reference only and are not guaranteed or tested.

cal valued are measured at VCC = VCC(TYP.) and TA = 25

Typi

25µA for special request

4.

I

AUG/09, v 1.4 Alliance Memory Inc

CC

- 0.2V

*4

?

Page 3 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

C

-

6

pF

Input/Output Capacitance

C

-

8

pF

Input Pulse Levels

0.2V to V

CC

- 0.2V

Input Rise and Fall Times

3ns

Input and Output Timing Reference Levels

1.5V

Output Load

CL = 30pF + 1TTL, IOH/I

= -2mA/4mA

PARAMETER

SYM.

AS6C4008-55

UNIT

MIN.

MAX.

Read Cycle Time

t

55

-

ns

Address Access Time

t

-

55

ns

Chip Enable Access Time

t

-

55

ns

Output Enable Access Time

t

-

30

ns

Chip Enable to Output in Low-Z

t

*

10

-

ns

Output Enable to Output in Low-Z

t

*

5

-

ns

Chip Disable to Output in High-Z

t

*

-

20

ns

Output Disable to Output in High-Z

t

*

-

20

ns

Output Hold from Address Change

t

10

-

ns

AS6C4008-55

UNIT

MIN.

MAX.

Write Cycle Time

t

55

-

ns

Address Valid to End of Write

t

50

-

ns

Chip Enable to End of Write

t

50 -

ns

Address Set-up Time

t

0

-

ns

Write Pulse Width

t

WP

45 -

ns

Write Recovery Time

t

0 -

ns

Data to Write Time Overlap

t

25 -

ns

Data Hold from End of Write Time

t

0

ns

Output Active from End of Write

tOW*

5

-

ns

Write to Output in High-Z

t

*

-

20

ns

CAPACITANCE (TA = 25℃, f = 1.0MHz)

IN

I/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

OL

RC AA

ACE

OE CLZ OLZ CHZ

OHZ

OH

(2) WRITE CYCLE

PARAMETER SYM.

WC

AW

CW

AS

WR DW

DH

WHZ

*These parameters are guaranteed by device characterization, but not production tested.

AUG09 v1.4 Alliance Memory Inc Page 4 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout

Previous Data Valid

tAA tOH

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

tRC

Address

CE#

OE#

Dout

tAA

tACE

tOE tOH

tOLZ

tCLZ

High-Z

Data Valid

tCHZ

tOHZ

High-Z

Notes :

1.

WE# is high for read cycle.

2.

Device is continuously selected OE# = low, CE# = low.

3.

Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.

4.t

CLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

5.At any gi

ven temperature and voltage condition, t

is less than t

CHZ

CLZ

, t

OHZ

is less than t

OLZ.

AUG09 v1.4 Alliance Memory Inc Page 5 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

W

RITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

tWC

Address

tAW

CE#

tCW

tAS

WE#

WHZ

t

Dout

Din Data Valid

(4)

tWP tWR

High-Z

tDW tDH

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

tWC

Address

tAW

T

OW

(4)

CE# tAS tWR

tCW

tWP

WE#

WHZ

t

Dout

Din Data Valid

Notes :

1.

WE#, CE# must be high during all address transitions.

2.

A write occurs during the overlap of a low CE#, low WE#.

3.

During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be

placed on

4.

During this period, I/O pins are in the output state, and input signals must not be applied.

5.

If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.

6.

tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

the bus.

(4)

High-Z

tDW tDH

AUG09 v1.4 Alliance Memory Inc Page 6 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

VCC for Data Retention

V

CE# ≧ V

- 0.2V

1.5 - 5.5

V

= 1.5V

-LL

- 2 30

µ

A

-LLE/-LLI

- 2 30

µ

A

Chip Disable to Data

See Data Retention

Recovery Time

t

- - ns

DATA RETENTION CHARACTERISTICS

DR

Data Retention Current

Retention Time

t

RC

= Read Cycle Time

*

I

DR

t

CDR

R

CC

CE# ≧ V

Waveforms (below)

DATA RETENTION WAVEFORM

Vcc

CE #

Vcc(min.)

CDR

t

V

IH

CC

- 0.2V

≧

1.5V

CC

V

DR

CE# ≧ Vcc-0.2V

0 - -

RC

*

Vcc(min.)

R

t

V

IH

ns

AUG09 v1.4 Alliance Memory Inc Page 7 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

UNIT

SYM.

A

0.118 (MAX)

2.997 (MAX)

A1

0.004(MIN)

0.102(MIN)

A2

0.111(MAX)

2.82(MAX)

b

0.016(TYP)

0.406(TYP)

c

0.008(TYP)

0.203(TYP)

D

0.817(MAX)

20.75(MAX)

E

0.445 ±0.005

11.303 ±0.127

E1

0.555 ±0.012

14.097 ±0.305

e

0.050(TYP)

1.270(TYP)

L

0.0347 ±0.008

0.881 ±0.203

L1

0.055 ±0.008

1.397 ±0.203

S

0.026(MAX)

0.660 (MAX)

y

0.004(MAX)

0.101(MAX)

Θ

0o -10

o

0o -10

o

PACKAGE OUTLINE DIMENSION

32 pin 450 mil SOP Package Outline Dimension

INCH.(BASE) MM(REF)

AUG09 v1.4 Alliance Memory Inc Page 8 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

UNIT

SYM.

A

0.047 (MAX)

1.20 (MAX)

A1

0.004 ±0.002

0.10 ±0.05

A2

0.039 ±0.002

1.00 ±0.05

0.008 + 0.002

- 0.001

0.20 + 0.05

-0.03

c

0.005 (TYP)

0.127 (TYP)

D

0.724 ±0.004

18.40 ±0.10

E

0.315 ±0.004

8.00 ±0.10

e

0.020 (TYP)

0.50 (TYP)

HD

0.787 ±0.008

20.00 ±0.20

L

0.0197 ±0.004

0.50 ±0.10

L1

0.0315 ±0.004

0.08 ±0.10

y

0.003 (MAX)

0.076 (MAX)

Θ

0

o

5

o

0

o

5

o

32

pin 8mm x 20mm TSOP-I Package Outline Dimension

b

INCH(BASE) MM(REF)

～

AUG09 v1.4 Alliance Memory Inc Page 9 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

A

A2

c

e b E

0.254

UNIT

SYM.

A

0.049 (MAX)

1.25 (MAX)

A1

0.005 ±0.002

0.130 ±0.05

A2

0.039 ±0.002

1.00 ±0.05

b

0.008 ±0.01

0.20±0.025

c

0.005 (TYP)

0.127 (TYP)

D

0.465 ±0.004

11.80 ±0.10

E

0.315 ±0.004

8.00 ±0.10

e

0.020 (TYP)

0.50 (TYP)

HD

0.528±0.008

13.40 ±0.20.

L

0.0197 ±0.004

0.50 ±0.10

L1

0.0315 ±0.004

0.8 ±0.10

y

0.003 (MAX)

0.076 (MAX)

Θ

0

o

5

o

0

o

5

o

32

pin 8mm x 13.4mm STSOP Package Outline Dimension

1

HD

cL

32

12° (2x) 12° (2x)

16

D

16

1 32

INCH(BASE) MM(REF)

17

"A"

A1

"A" DETAIL VIEW

Seating Plane

SEATING PLANE

y

12° (2X)

L1

L

GAUGE PLANE

0

AUG09 v1.4 Alliance Memory Inc Page 10 of 14

～

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

36 ball 6mm × 8mm TFBGA Package Outline Dimension

AUG09 v1.4 Alliance Memory Inc Page 11 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

32

-pin 400mil TSOP-Ⅱ Package Outline Dimension

AUG/09, v 1.0.a Alliance Memory Inc Page 12 of 14

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

32 pin 600 mil P-DIP Package Outline Dimension

UNIT

SYM.

A1

A2

B

0.018 ± 0.005

0.457 ± 0.127

D

1.650 ± 0.005

41.910 ± 0.127

E

0.600 ± 0.010

15.240 ± 0.254

E1

e

0.100 (TYP)

2.540 (TYP)

eB

0.640 ± 0.020

16.256 ± 0.508.

L

0.130 ± 0.010

3.302 ± 0.254

S

0.075 ± 0.010

1.905 ± 0.254

Q1

0.070 ± 0.005

1.778 ± 0.127

INCH(BASE) MM(REF)

0.015 (MIN) 0.381 (MIN)

0.155 ± 0.005 3.937 ± 0.127

0.545 ± 0.005 13.843 ± 0.127

Note : D/E1/S dimension do not include mold flash.

AUG09 v1.4 Alliance Memory Inc

Page 13 of 14

AUGUST 2009

Alliance

Organization

VCC

Package

Operating

Temp

Speed

ns

AS6C4008-55PCN

512k x 8

5V

32pin 600mil DIP

Commercial ~ 0º C to 70º C

55

AS6C4008-55SIN

512k x 8

5V

32pin 450mil SOP

Industrial ~

-40ºC to 85º C

55

AS6C4008-55TIN

512k x 8

5V

32pin TSOP 1 (8 x 20 mm)

-40ºC to 85º C

55

AS6C4008-55STIN

512k x 8

5V

32pin sTSOP (8 x 13.4 mm)

Industrial ~

-40ºC to 85º C

55

AS6C4008-55BIN

512k x 8

5V

36pin TFBGA (6mm x 8mm)

Industrial ~

-40ºC to 85º C

55

5V

32-pin 400mil TSOP 11

Industrial ~

-40ºC to 85º C

55

AS6C

4008

- 55

X

N

low

Device

Access

Package Options:

Temperature Range:

N = Lead

P = 32 pin 600 mil P-DIP

S = 32 pin 450 mil SOP

T = 32 pin TSOP 1 (8mm x 20 mm)

C = Commercial

power

Number

Z = 32-pin 400mil TSOP 11

(0ºC to +70º C)

Free ROHS

SRAM

40 = 4M

ST = 32 pin sTSOP (8mm x 13.4 mm)

I = Industrial

Compliant

prefix

08 = by 8

Time

B = 36 pin TFBGA (6mm x 8mm)

(-40º to +85º C)

Part

512K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

AS6C4008

Industrial ~

AS6C4008-55ZIN

512k x 8

PART NUMBERING SYSTEM

AUG09 v1.4 Alliance Memory Inc Page 14 of 14