ALLIANCE 628512-55 55$#SAM

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K6X4008C1F Family

Document Title

512Kx8 bit Low Power full CMOS Static RAM

Revision History

CMOS SRAM

Revision No.

0.0

0.1

1.0

History

Initial draft

Revised

- Added Commercial Product.

Finalized

- Added Lead Free 32-SOP-525 Product

- Changed ICC from 10mA to 5mA

- Changed ICC1 from 8mA to 7mA

- Changed ICC2 from 40mA to 30mA

- Changed ISB from 3mA to 0.4mA

- Changed IDR(Commercial) from 15µA to 12µA

- Changed IDR(industrial) from 20µA to 12µA

- Changed IDR(Automotive) from 30µA to 25µA

Draft Date

July 30, 2002

November 30, 2002

September 16, 2003

Remark

Preliminary

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

September 2003

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K6X4008C1F Family

512Kx8 bit Low Power full CMOS Static RAM

CMOS SRAM

FEATURES

• Process Technology: Full CMOS

• Organization: 512Kx8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL compatible

• Package Type: 32-DIP-600, 32-SOP-525,

32-TSOP2-400F/R

GENERAL DESCRIPTION

The K6X4008C1F families are fabricated by SAMSUNG′s advanced full CMOS process technology. The families supports various operating temperature range and various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.

PRODUCT FAMILY

Power Dissipation

Product Family Operating Temperature Vcc Range Speed

Standby

(ISB1, Max)

Operating

(ICC2, Max)

K6X4008C1F-B Commercial (0~70°C)

20µA

K6X4008C1F-F Industrial (-40~85°C)

4.5~5.5V

551)/70ns

30mA

K6X4008C1F-Q Automotive (-40~125°C) 30µA 32-SOP-525, 32-TSOP2-400F

1. The parameter is measured with 50pF test load.

PIN DESCRIPTION

A18 A16 A14 A12

I/O1 I/O2 I/O3 VSS

A7 A6 A5 A4 A3 A2 A1 A0

32-DIP

32-SOP

32-TSOP2

(Forward)

VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4

VCC

A15 A17

A13

A11

A10 CS I/O8 I/O7 I/O6 I/O5 I/O4

32-TSOP2

(Reverse)

A18

A16

A14 A12

VSS

A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Row Addresses

I/O1 I/O8

Row select

Data cont

PKG Type

32-DIP-600, 32-SOP-525,

32-TSOP2-400F/R

Precharge circuit.

Memory array

I/O Circuit

Column select

Pin Name Function

Column Addresses

WE Write Enable Input

CS Chip Select Input OE Output Enable Input

A0~A18 Address Inputs

Control logic

I/O1~I/O8 Data Inputs/Outputs

Vcc Power Vss Ground

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

September 2003

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K6X4008C1F Family

CMOS SRAM

PRODUCT LIST

Commercial Products(0~70°C) Industrial Products(-40~85°C) Automotive Products(-40~125°C)

Part Name Function Part Name Function Part Name Function

K6X4008C1F-DB55 K6X4008C1F-DB70 K6X4008C1F-GB55 K6X4008C1F-GB70 K6X4008C1F-BB55 K6X4008C1F-BB70 K6X4008C1F-VB55 K6X4008C1F-VB70 K6X4008C1F-MB55 K6X4008C1F-MB70

1. Lead Free Product

32-DIP, 55ns, LL 32-DIP, 70ns, LL 32-SOP, 55ns, LL 32-SOP, 70ns, LL

32-SOP, 55ns, LL

32-SOP, 70ns, LL 32-TSOP2-F, 55ns, LL 32-TSOP2-F, 70ns, LL 32-TSOP2-R, 55ns, LL 32-TSOP2-R, 70ns, LL

K6X4008C1F-DF55 K6X4008C1F-DF70 K6X4008C1F-GF55 K6X4008C1F-GF70 K6X4008C1F-BF55 K6X4008C1F-BF70 K6X4008C1F-VF55 K6X4008C1F-VF70 K6X4008C1F-MF55 K6X4008C1F-MF70

32-DIP, 55ns, LL 32-DIP, 70ns, LL 32-SOP, 55ns, LL 32-SOP, 70ns, LL

32-SOP, 55ns, LL

32-SOP, 70ns, LL 32-TSOP2-F, 55ns, LL 32-TSOP2-F, 70ns, LL 32-TSOP2-R, 55ns, LL 32-TSOP2-R, 70ns, LL

K6X4008C1F-GQ55 K6X4008C1F-GQ70 K6X4008C1F-VQ55 K6X4008C1F-VQ70

32-SOP, 55ns, L 32-SOP, 70ns, L 32-TSOP2-F, 55ns, L 32-TSOP2-F, 70ns, L

FUNCTIONAL DESCRIPTION

CS OE WE I/O Pin Mode Power

L H H High-Z Output disbaled Active L L H Dout Read Active L

1. X means don′t care.( Must be in low or high state.)

High-Z Deselected Standby

L Din Write Active

ABSOLUTE MAXIMUM RATINGS

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5V(max. 7.0V) V Voltage on Vcc supply relative to Vss VCC -0.3 to 7.0 V Power Dissipation PD 1.0 W Storage temperature TSTG -65 to 150 °C -

Operating Temperature TA

0 to 70

-40 to 85 K6X4008C1F-F

°C

K6X4008C1F-B

-40 to 125 K6X4008C1F-Q

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

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September 2003

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K6X4008C1F Family

CMOS SRAM

-0.5

Vcc+0.5

- 0.8 V

RECOMMENDED DC OPERATING CONDITIONS

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 Input low voltage VIL

Note:

1.Commercial Product: TA=0 to 70°C, otherwise specified Industrial Product: TA=-40 to 85°C, otherwise specified

Automotive Product: TA=-40 to 125°C, otherwise specified

2. Overshoot: VCC+3.0V in case of pulse width ≤ 30ns

3. Undershoot: -3.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE

Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF

1. Capacitance is sampled, not 100% tested

(f=1MHz, TA=25°C)

Item Symbol Test Condition Min Max Unit

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 5 mA

Cycle time=1µs, 100% duty, IIO=0mA

ICC1

Average operating current

Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or VIH - - 0.4 mA

Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc

CS≤0.2V, VIN≥0.2V or VIN≥Vcc-0.2V

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

ICC2

K6X4008C1F-B - K6X4008C1F-F - K6X4008C1F-Q - - 30 µA

- - 7 mA

- - 30 mA

20 µA

Revision 1.0

September 2003

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K6X4008C1F Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=50pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS

(Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)

Speed Bins

Read

Write

Parameter List Symbol

Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns

55ns 70ns

Min Max Min Max

Units

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 - 5.5 V

K6X4008C1F-B

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V

Data retention set-up time tSDR Recovery time tRDR 5 - -

See data retention waveform

K6X4008C1F-F 12 K6X4008C1F-Q 25

- -

0 - -

Revision 1.0

September 2003

µA

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K6X4008C1F Family

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

tOLZ

Data out

High-Z

tLZ

tAA

tRC

tAA

tCO1

tOE

CMOS SRAM

Data Valid

tOH

tHZ

tOHZ

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

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September 2003

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K6X4008C1F Family

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

tAS(3)

Data in

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

Data Undefined

tAS(3)

tAW

tWHZ

tWC

tCW(2)

tAW

tWC

tCW(2)

tWP(1)

tDW

Data Valid

CMOS SRAM

tWR(4)

tDH

tOW

tWR(4)

tDW

Data in

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

High-Z

Data Valid

tDH

High-Z

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

tSDR

Data Retention Mode

tRDR

CS GND

CS≥VCC - 0.2V

Revision 1.0

September 2003

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K6X4008C1F Family

CMOS SRAM

PACKAGE DIMENSIONS

32 PIN DUAL INLINE PACKAGE (600mil)

#32

13.60±0.20

0.535±0.008

0.46±0.10

1.91

( )

0.075

0.018±0.004

1.52±0.10

0.060±0.004

42.31

MAX

1.666

41.91±0.20

1.650±0.008

2.54

0.100

#17

#16

15.24

0.600

3.81±0.20

0.150±0.008

0.200

0.38

MIN

0.015

5.08

MAX

3.30±0.30

0.130±0.012

Units : millimeter(Inch)

+0.10

0.25

-0.05 +0.004

0.010

-0.002

0~15°

32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)

#32

0.71

( )

0.028

0.41

0.016

20.47±0.20

0.806±0.008

+0.100

-0.050 +0.004

-0.002

20.87

0.822

MAX

1.27

0.050

#17

#16

14.12±0.30

0.556±0.012

2.74±0.20

0.108±0.008

3.00

0.118

0.05

MIN

0.002

11.43±0.20

0.450±0.008

MAX

+0.10

0.20

-0.05 +0.004

0.008

-0.002

0.10 MAX

0.004 MAX

0~8°

13.34

0.525

0.80±0.20

0.031±0.008

Revision 1.0

September 2003

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K6X4008C1F Family

CMOS SRAM

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

#32

21.35

MAX

0.841

20.95±0.10

0.825±0.004

#17

#16

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

0.047

1.20

MAX

0.25

( )

0.010

10.16

0.400

+0.10

0.15

-0.05 +0.004

0.006

-0.002

0.10 MAX

0.004 MAX

Units : millimeter(Inch)

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

0.95

( )

0.037

0.40±0.10

0.016±0.004

1.27

0.050

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

#32

21.35

MAX

0.841

20.95±0.10

0.825±0.004

#16

#17

0.05

MIN

0.002

11.76±0.20

0.463±0.008

1.00 ±0.10

0.039±0.004

1.20

0.047

MAX

0.25

( )

0.010

10.16

0.400

0.15

0.006

0.10 MAX

0.004 MAX

+0.10

-0.05

+0.004

-0.002

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

0.95

( )

0.037

0.40±0.10

0.016±0.004

1.27

0.050

0.05

MIN

0.002

Revision 1.0

September 2003