ALLEGRO UDN 2987 LWTR-6T Datasheet

UDN2987x-6

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

Features and Benefits

▪ 4.75 to 35 V driver supply voltage
▪ Output enable-disable (OE/R)
▪ 350 mA output source current
▪ Overcurrent protected
▪ Internal ground clamp diodes
▪ Output Breakdown Voltage 35 V minimum
▪ TTL, DTL, PMOS, or CMOS compatible inputs
▪ Internal Thermal Shutdown (TSD)

Package: 20-pin SOICW (suffix LW)

Not to scale

Description

Providing overcurrent protection for each of its eight
sourcing outputs, the UDN2987LW-6 driver is used as an
interface between standard low-level logic and relays, motors,
solenoids, LEDs, and incandescent lamps. This device includes
thermal shutdown and output transient protection/clamp diodes
for use with sustaining voltages to 35 V.

In this driver, each channel includes a latch to turn off that
channel if the maximum channel current is exceeded. All
channels are disabled if the thermal shutdown is activated. A
common FAULT output is used to indicate either chip thermal
shutdown or any overcurrent condition. All outputs are enabled

by pulling the common OE/R input high. When OE/R ¯ is low,
all outputs are inhibited and the eight latches are reset. The

OE/R ¯function can be especially important during power-up,
in preventing floating inputs from turning on the outputs.

Under normal operating conditions, each of eight outputs
will source in excess of 100 mA continuously at an ambient
temperature of 25°C and a supply of 35 V. The overcurrent
fault circuit will protect the device from short-circuits to ground
with supply voltages of up to 30 V.

T ypical Application

IN1

IN2

IN3

IN4

CPU

IN5

IN6

IN7

IN8

FAULT
OE/R

2987

¯

Continued on the next page…

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

GND

VS

1 to 8 Load
Components

4.75 to 35 V

29876-DS, Rev. 6

UDN2987x-6

Description (continued)

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

The inputs are compatible with 5 and 12 V logic systems: TTL,
Schottky TTL, DTL, PMOS, and CMOS. In all cases, the output is
switched ON by an active high input level. Compared to predecessor
devices, the UDN2987LW-6 has a significantly faster T

PHL

(200 ns

The UDN2987LW-6 is supplied in a 20-lead small-outline (SOIC-W)
plastic package. All packages are lead (Pb) free, with 100% matte­tin leadframe plating.

typical) and a lower driver supply voltage rating (4.75 V), which
allows the use of 5 V logic.

Selection Guide

Part Number Packing Package

UDN2987LWTR-6-T 1000 pieces/13-in. reel 20-pin SOIC, wide body

Absolute Maximum Ratings

Parameter Symbol Notes Rating Units

Supply Voltage V
Continuous Output Current* I
FAULT Output Voltage V
FAULT Output Current I
Input Voltage V
Junction Temperature T
Storage Temperature Range T
Operating Temperature Range T

*For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.

S

OUT

CE

C

IN

J

S

A

Outputs are disabled at approximately –500 mA –500 mA

Range N –55 to 150 °C

35 V

35 V
30 mA

–0.3 to 14 V

150 °C

–20 to 85 °C

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

2

UDN2987x-6

DABIC-5 8-Channel Source Driver

Functional Block Diagram

VS

Thermal

Shut Down

with Overcurrent Protection

¯

OE/R

IN1

IN8

Pin-Out Diagram

1

IN1

2

IN2

3

IN3

4

IN4

5

IN5

6

IN6

7

IN7

8

IN8

FAULT

OE/R

9

10

x8

OEN

OE

FF

SENSEN

20

19

18

17

16

15

14

13

12

11

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

GND

VS

Dwg. PP-067

RS

Q

<1Ω

+

–

Driver 1 of 8 drivers

GND

Terminal List Table

Number Name Description

FAULT

OUT1

OUT8

1 IN1 Logic input 1
2 IN2 Logic input 2
3 IN3 Logic input 3
4 IN4 Logic input 4
5 IN5 Logic input 5
6 IN6 Logic input 6
7 IN7 Logic input 7
8 IN8 Logic input 8

9 FAULT Fault output
10 OE/ ¯R¯ Logic input for Output Enable and Reset
11 VS Supply voltage
12 GND Supply ground
13 OUT8 Output 8 to load
14 OUT7 Output 7 to load
15 OUT6 Output 6 to load
16 OUT5 Output 5 to load
17 OUT4 Output 4 to load
18 OUT3 Output 3 to load
19 OUT2 Output 2 to load
20 OUT1 Output 1 to load

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

3

UDN2987x-6

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

ELECTRICAL CHARACTERISTICS, valid at T

= 25°C, V

A

= 2.4 V, VS = 35 V, unless otherwise noted

OER

Characteristic Symbol Test Conditions Min. Typ.1Max. Units

Supply Voltage Functional Range V

Output Leakage Current

Output Sustaining Voltage V

Output Saturation Voltage V

Channel Shut Down Threshold

2

2

I

OUTCEXVIN

OUT(sus)IOUT

OUT(SAT)

FAULT Leakage Current I

FAULT Saturation Voltage V

Input Voltage

CE(SAT)IC

V

V

IN(OFF)

S

I

M

CEX

IN(ON)

= 0.4 V, all inputs simultaneously – 200 <–5.0 – μA

= –350 mA, L = 2.0 mH 35 — — V

VIN = 2.4 V, I

V

= 2.4 V, I

IN

VIN = 2.4 V, I

= –100 mA — 1.6 1.8 V

OUT

= –225 mA — 1.7 1.9 V

OUT

= –350 mA — 1.8 2.0 V

OUT

VIN = 2.4 V, Vs = 30 V – –500 – 370 mA

VCC = 35 V — <1.0 100 μA

= 30 mA — 0.3 0.8 V

4.75 — 35 V

2.4 — — V

— — 0.4 V

VIN = 2.4 V — — 100 μA

I

Input Current: INx, OE/R

¯ pins

IN(ON)

I

IN(OFF)

Clamp Diode Leakage Current I

Clamp Diode Forward Voltage V

I

Supply Current

Thermal Shut Down T

Thermal Hysteresis T

Reset Pulse Duration t

Propagation Delay Time

Blank Time t

1

Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-

vidual units, within the specified maximum and minimum limits.

2

For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.

S(ON)

I

S(OFF)

JTSD

JTSDhys

RPD

t

PLH

t

PHL

BLANK

VIN = 5.0 V — — 600 μA

VIN = 12 V — — 1000 μA

VIN = 0.4 V — — 15 μA

VR = 35 V, TA = 70°C — — 50 μA

R

IF = 350 mA — 1.5 1.8 V

F

VIN = 2.4 V, all inputs simultaneously; outputs open — 7.0 18 mA

VIN = 0.4 V, all inputs simultaneously — 6.0 12 mA

— 165 — °C

—15—°C

1.0 — — μs

VS = 35 V, RL = 100 Ω, C

VS = 35 V, RL = 100 Ω, C

= 30 pF — 100 600 ns

LOAD

= 30 pF — 200 1000 ns

LOAD

— 1.0 — μs

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

4

UDN2987x-6

THERMAL CHARACTERISTICS

Characteristics Symbol Test Conditions Rating Unit

Package Thermal Resistance

*

Additional thermal information is available on the Allegro Web site.

*

4.0

R

θJA

Power Dissipation versus Ambient Temperature

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

Package LW, on 4-layer board based on JEDEC standard 48 °C/W

3.5

3.0

2.5

(W)

D

2.0

P

1.5

1.0

0.5

0

25 50 75 100 125 150

Package LW

(R

QJA

= 48 ºC/W)

TA (°C)

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

5

UDN2987x-6

V

IN(A)

= V

I

I

IN(B)

OE/R

I

SH

OUT(A)

I

OUT(B)

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

Characteristic Performance

Output Current Waveshapes

t

—

M

PLH

Output (A) shorted

t

BLANK

Momentary fault or capacitive charging (<1μs)

t

RTB

t

PHL

Allowable Output Current as a Function of Duty Cycle

(Multiply by 78% for UDN2987LW-6)

TA= 25°C, VS = 35 V TA= 50°C, VS = 35 V

400

350

300

250

200

150

Collector Current (mA)

100

50

0

0 10 20 30 40 50 60 70 80 90 100

Quantity of outputs conducting simultaneously

87 6 5 4 3

Duty Cycle (%)

400

350

300

250

200

150

Collector Current (mA)

100

50

0

0 10 20 30 40 50 60 70 80 90 100

Quantity of outputs conducting simultaneously

876 5 4 3 2

Duty Cycle (%)

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

6

UDN2987x-6

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

Applications Information and Circuit Description

As with all power integrated circuits, the UDN2987LW-6
has a maximum allowable output current rating. The
500 mA rating does not imply that operation at that value
is permitted or even obtainable. The channel output current
trip point is specified as –370 mA, minimum; therefore,
attempted operation at current levels greater than –370 mA
may cause a fault indication and channel shutdown. The
device is tested at a maximum of –350 mA and that is the
recommended maximum output current per driver. It pro­vides protection for current overloads or shorted loads up to
30 V.

All outputs are enabled by pulling the OE/R ¯ input high.
When OE/R ¯ is low or allowed to float (internal pull-down),
all outputs are inhibited and the latches are reset. Note that
the reset pulse duration (OE/R ¯ low) should be at least 1 μs.
This will ensure safe operation under attempted reset condi­tions with a shorted load. The latches are also reset during
power-up, regardless of the state of the OE/R ¯ input.

The load current causes a small voltage drop across the
internal low-value sense resistor. This voltage is com-

pared to the voltage drop across a reference resistor with
a constant current. The two resistors are matched to
eliminate errors due to manufacturing tolerances or tem­perature effects. Each channel includes a comparator and
its own latch. An overcurrent fault (V

SENSE

> V

REF

) will
set the affected latch and shut down only that channel.
All other channels will continue to operate normally. The
latch includes a 1 μs blanking delay, t

BLANK

, to prevent
unwanted triggering due to crossover currents generated
when switching inductive loads. For an abrupt short circuit,
the blanking and output switching times will allow a brief,
permissible current in excess of the trip current before the
output driver is turned off.

A common thermal shutdown disables all outputs if the
chip temperature exceeds 165°C. At thermal shutdown, all
latches are reset. The outputs are disabled until the chip
cools down to approximately 150°C (thermal hysteresis).

In the event of an overcurrent condition on any channel, or
chip thermal shutdown, the FAULT open-collector output is
pulled low (turned on).

Overcurrent Fault Sense Circuit

+

V

REF

Matched

–

To Fault Latch

–

+

SENSE

REF

I

REF

V

I

LOAD

S

+

V

SENSE

–

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

7

UDN2987x-6

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

Package LW, 20-pin SOIC-W

20X

C0.10

0.41 ±0.10

12.80±0.20

20

10.30±0.33

7.50±0.10

A

21

SEATING
PLANE

1.27

For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

2.65 MAX

0.20 ±0.10

4° ±4

+0.07

0.27

–0.06

+0.44

0.84

–0.43

0.25

C

SEATING PLANE

GAUGE PLANE

Terminal #1 mark area

A

Reference pad layout (reference IPC SOIC127P1030X265-20M)

B

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances

2.25

20

21

PCB Layout Reference View

B

0.65

9.50

1.27

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

8

UDN2987x-6

Revision History

DABIC-5 8-Channel Source Driver

with Overcurrent Protection

Revision Revision Date Description of Revision

Rev. 6 April 30, 2012 Update product availability

Copyright ©2006-2012, Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per­mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

9