Allegro UCQ5818EPF, UCQ5818AF Datasheet

26182.29A

5818-F

BiMOS II 32-BIT SERIAL-INPUT, LATCHED

Data Sheet

SOURCE DRIVERS FOR -40

UCQ5818EPF

30

32

31

OUT

OUT

OUT

OUT

OUT

OUT

NC

6

5

4

7

29

8

9

10

11

12

13

14

15

16

17

19

LATCHES

REGISTER

20

18

19

17

18

NC

OUT

OUT

SERIAL

3

2

BLNK

21

22

GROUND

BLANKING

LOAD

DATA OUT

1

BB

V

CLK

23

CLOCK

SUPPLY

ABSOLUTE MAXIMUM RATINGS

at TA = 25°C

Logic Supply Voltage, VDD.................... 15 V

Driver Supply Voltage, V
Continuous Output Current,

I

......................... -40 mA to +15 mA

OUT

Input Voltage Range,

VIN....................... -0.3 V to V

Package Power Dissipation, P

(UCQ5818AF) ............................ 3.5 W*

(UCQ5818EPF) ......................... 2.7 W†

Operating Temperature Range,

T

................................. -40°C to +85°C

A

Storage Temperature Range,

T

............................... -55°C to +150°C

S

* Derate at rate of 28 mW/°C above TA = +25°C
† Derate at rate of 22 mW/°C above TA = +25°C

Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.

BB

1

3

2

OUT

OUT

OUT

SERIAL

DATA IN

LOGIC

SUPPLY

43

44

DD

V

ST

24

STROBE

OUT

25

16

42

REGISTER

OUT

26

15

OUT

41

2

LATCHES

8

27

14

OUT

40

28

NC

................... 60 V

+ 0.3 V

DD

D

OUT

39

38

37

36

35

34

33

19

32

31

OUT

30

NC

29

Dwg. PP-059-2

°

C TO +85°C OPERATION

Designed primarily for use with vacuum-fluorescent displays, the
UCQ5818AF and UCQ5818EPF smart power BiMOS II drivers combine
CMOS shift registers, data latches, and control circuitry, with bipolar high­speed sourcing outputs and DMOS active pull-down circuitry. The high­speed shift register and data latches allow direct interfacing with microproces­sor LSI-based systems. A CMOS serial data output enables cascade connec-

4

tions in applications requiring additional drive lines. Both devices feature 60
V and -40 mA output ratings, allowing them to be used in many other
peripheral power driver applications.

These smart power drivers have been designed with BiMOS II logic for
improved data entry rates. With a 5 V supply, they will operate to at least

3.3 MHz. At 12 V, higher speeds are possible. Use of these devices with
TTL may require the use of appropriate pull-up resistors to ensure an input
logic high. All devices can be operated over the ambient temperature range of

13

-40°C to +85°C. The UCQ5818AF is supplied in a 40-pin plastic dual in-line
package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced
supply current requirement, and low output saturation voltage permits
operation with minimum junction temperature rise. The ‘A’ package allows
all 32 outputs to be operated at -25 mA continuously over the operating
temperature range.

For high-density packaging applications, the UCQ5818EPF is furnished
in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder
lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous
operation of all outputs simultaneously at ambient temperatures to 60°C.
Similar devices are available as the UCQ5810AF/LWF (10 bits), UCQ5811A
(12 bits), and UCQ5812AF/EPF (20 bits).

FEATURES

■ 60 V Source Outputs

■ High-Speed Source Drivers

■ To 3.3 MHz Data Input Rate

■ Low-Output Saturation Voltages

■ Active DMOS Pull-Downs

Always order by complete part number, e.g., UCQ5818EPF .

■ Low-Power CMOS Logic
and Latches

■ Reduced Supply Current
Requirements

■ Improved Replacements for
SN75518N/FN

5818-F

Dwg. FP-013-1

SERIAL
DATA OUT

32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION

UCQ5818AF

LOAD

SUPPLY

SERIAL

DATA OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BLANKING

GROUND

1

V

BB

2

338

32

4

31

5

30

6

29

7

28

8

27

9

26

10

25

LATCHES

11

24

12

23

13

22

14

21

15

20

16

19

17

18

18

17

19

BLNK

20

REGISTER

LATCHES

REGISTER

V

CLK

LOGIC

40

DD

SUPPLY

SERIAL

39

DATA IN

OUT

1

37

OUT

2

OUT

36

3

OUT

35

4

OUT

34

5

33

OUT

6

32

OUT

7

31

OUT

8

30

OUT

9

29

OUT

10

28

OUT

11

27

OUT

12

26

OUT

13

25

OUT

14

24

OUT

15

23

OUT

16

22

STROBE

ST

21

CLOCK

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

GROUND

FUNCTIONAL BLOCK DIAGRAM

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

OUT1OUT

OUT

2

3

OUT

N

TYPICAL INPUT CIRCUIT

V

DD

IN

V

DD

MOS

BIPOLAR

V

BB

LOGIC
SUPPLY

LOAD
SUPPLY

Dwg. PP-029-4

3.0

2.5

SUFFIX 'A', R = 36°C/W

θJA

2.0

1.5

SUFFIX 'EP', R = 46°C/W

θJA

1.0

0.5

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

0

25

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

Dwg. GP-025A

Dwg. GP-025A

Dwg. EP-010-5

TYPICAL OUTPUT DRIVER

V

BB

OUT

N

Dwg. No. A-14,219

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Copyright © 1988, 2000 Allegro MicroSystems, Inc.

5818-F

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

FOR -40°C TO +85°C OPERATION

ELECTRICAL CHARACTERISTICS over operating temperature range, VBB = 60 V unless other­wise noted.

Limits @ VDD = 5 V Limits @ VDD = 12 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

V

Output Leakage Current I

Output Voltage V

Output Pull-Down Current I

Input Voltage V

Input Current I

Serial Data Output Voltage V

Maximum Clock Frequency f

Supply Current I

Blanking to Output Delay t

Output Fall Time t

Output Rise Time t

CEX

OUT(1)IOUT

V

OUT(0)IOUT

OUT(0)

IN(1)

V

IN(0)

IN(1)

I

IN(0)

OUT(1)IOUT

V

OUT(0)IOUT

clk

DD(1)

I

DD(0)

I

BB(1)

I

BB(0)

PHL

t

PLH

f

r

= 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA

OUT

= -25 mA 58 58.5 — 58 58.5 — V

= 1 mA — 2.0 3.0 ——— V

= 2 mA ——— —2.0 3.5 V

I

OUT

V

= 5 V to V

OUT

= 20 V to V

V

OUT

VIN = V

DD

VIN = 0.8 V — -0.05 -0.5 — -0.1 -1.0 µA

= -200 µA 4.5 4.7 — 11.7 11.8 — V

= 200 µA — 200 250 — 100 200 mV

All Outputs High — 100 300 — 200 500 µA

All Outputs Low — 100 300 — 200 500 µA

Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA

Outputs Low — 10 100 — 10 100 µA

CL = 30 pF, 50% to 50% — 2000 ——1000 — ns

CL = 30 pF, 50% to 50% — 1000 ——850 — ns

CL = 30 pF, 90% to 10% — 1450 ——650 — ns

CL = 30 pF, 10% to 90% — 650 ——700 — ns

BB

BB

2.0 3.5 — ——— mA

——— 8.0 13 — mA

3.5 — 5.3 10.5 — 12.3 V

-0.3 — +0.8 -0.3 — +0.8 V

— 0.05 0.5 — 0.1 1.0 µA

3.3* —— ——— MHz

Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

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