Allegro UCQ5815EP, UCQ5815A Datasheet

Designed primarily for use with high-voltage vacuum-fluorescent displays, the UCN5815A and UCN5815EP BiMOS II integrated circuits consist of eight npn Darlington source drivers with output pull­down resistors, a CMOS latch for each driver, and common STROBE, BLANKING, and ENABLE functions.
BiMOS II devices have considerably better data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will operate to at least 4.4 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs cause minimum loading and are compatible with standard CMOS and NMOS logic commonly found in microprocessor designs. TTL circuits may require the use of appropri­ate pull-up resistors.
The bipolar outputs may be used as segment, dot (matrix), bar, or digit drivers in vacuum-fluorescent displays. All eight outputs can be activated simultaneously at ambient temperatures in excess of 75°C. To simplify printed wiring board layout, output connections are opposite the inputs. A minimum component display subsystem, requiring few or no discrete components, can be assembled using the UCN5815A/EP with the UCN5810AF/EPF/LWF, UCN5812AF/EPF, or UCN5818AF/EPF serial-to-parallel latched drivers.
Suffix ‘A’ devices are furnished in a standard 22-pin plastic DIP; suffix ‘EP’ indicates a 28-lead PLCC.
BiMOS II 8-BIT
LATCHED SOURCE DRIVERS
UCN5815A
FEATURES
To 4.4 MHz Date-lnput Rate
High-Voltage Source Outputs
CMOS, NMOS, TTL Compatible Inputs
Low-Power CMOS Latches
Internal Pull-Down Resistors
Wide Supply-Voltage Range
Always order by complete part number:
Part Number Package
UCN5815A 22-Pin DIP
UCN5815EP 28-Lead PLCC
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, V
OUT
. . . . . . . . . . . . . . 60 V
Logic Supply Voltage Range,
V
DD
. . . . . . . . . . . . . . . . . . 4.5 V to 15 V
Load Supply Voltage Range,
VBB. . . . . . . . . . . . . . . . . . 5.0 V to 60 V
Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Output Current,
I
OUT
. . . . . . . . . . . . . . . . . . . . . . -40 mA
Package Power Dissipation, P
D
(UCN5815A) . . . . . . . . . . . . . . . 2.5 W*
(UCN5815EP) . . . . . . . . . . . . . 2.27 W*
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
TS. . . . . . . . . . . . . . . . -55°C to +150°C
* Derate linearly to 0 W at +150°C.
Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
Data Sheet
26183.10A*
5815
221
22
LOGIC SUPPLY
ENABLE
1 BLANKING
STROBE
V
DD
3
4
5
6
7
16
17
18
19
20
OUT
1
OUT
2
OUT
3
OUT
4
IN
1
IN
2
IN
3
IN
4
7
8
9
10
11
12
13
14
15
GROUND
OUT
5
OUT
6
OUT
7
Dwg. PP-015-3
OUT
8
LOAD SUPPLY
IN
5
IN
6
IN
7
IN
8
LATCHES
V
BB
5815
BiMOS II 8-BIT LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V, VDD = 5 V and 12 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Max. Units
Output Off Voltage V
OUT
1.0 V
Output On Voltage V
OUT
I
OUT
= -25 mA, VBB = 60 V 57.5 V
Output Pull-Down Current I
OUT
V
OUT
= V
BB
400 850 µA
Output Leakage Current I
OUT
TA = 70°C -15 µA
Input Voltage V
IN(1)
VDD = 5.0 V 3.5 5.3 V
V
DD
= 12 V 10.5 12.3 V
V
IN(0)
-0.3 +0.8 V
Input Current I
IN(1)
VDD = VIN = 5.0 V 100 µA
V
DD
= VIN = 12 V 240 µA
Input lmpedance Z
IN
VDD = 5.0 V 50 k
Supply Current l
BB
All outputs on, All outputs open 10.5 mA
All outputs off, All outputs open 100 µA
l
DD
VDD = 5.0 V, All outputs off, All inputs = 0 V 100 µA
V
DD
= 12 V, All outputs off, All inputs = 0 V 200 µA
V
DD
= 5.0 V, One output on, All inputs = 0 V 1.0 mA
VDD = 12 V, One output on, All inputs = 0 V 3.0 mA
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
TYPICAL INPUT
CIRCUIT
TYPICAL OUTPUT
DRIVER
IN
V
DD
Dwg. No. EP-010-4A Dwg. No. EP-021-3
OUT
100 K
V
BB
Copyright © 1984, 2000 Allegro MicroSystems, Inc.
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