Allegro UCN5812EPF, UCN5812AF, UCQ5812EPF, UCQ5812AF Datasheet
26182.26B
5812-F
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
Data Sheet
UCN5812EPF
20
19
OUT
SERIAL
DATA OUT
LOAD
1
2
BB
V
REGISTER
CLK
14
15
CLOCK
GROUND
LOGIC
SUPPLY
28
V
ST
16
STROBE
DD
OUT
OUT
OUT
4
3
5
18
6
7
8
9
10
11
12
12
11
OUT
LATCHES
13
BLANKING
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD..................... 15 V
Driver Supply Voltage, V
Continuous Output Current Range,
I
................................. -40 to +15 mA
OUT
Input Voltage Range,
VIN........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, P
(UCN5812AF) ........................... 3.12 W*
(UCN5812EPF) ........................ 1.92 W†
Operating Temperature Range,
TA.................................. -20°C to +85°C
Storage Temperature Range,
TS................................ -55°C to +150°C
BB
1
OUT
SERIAL
DATA IN
SUPPLY
26
27
25
24
23
LATCHES
REGISTER
17
10
OUT
22
21
20
19
18
9
OUT
Dwg. PP-059-1
.................... 60 V
D
OUT
OUT
The UCN5812AF/EPF combine a 20-bit CMOS shift register, data
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, highcurrent outputs also allow them to be used in other peripheral power driver
applications. They are improved versions of the original UCN5812A/EP.
2
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
8
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5818AF/EPF
(32 bits).
The output source drivers are high-voltage pnp-npn Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
The UCN5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCN5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCN5812AF over the operating temperature range,
and the UCN5812EPF up to +75°C. All devices are also available for operation between -40°C and +85°C. To order, change the prefix from ‘UCN’ to
‘UCQ’.
* Derate at rate of 25 mW/°C above TA = +25°C
† Derate at rate of 15 mW/°C above TA = +25°C
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCN5812AF (dual in-line package)
and UCN5812EPF (PLCC package) are electrically identical and share a common terminal
number assignment.
FEATURES
■ High-Speed Source Drivers
■ 60 V Source Outputs
■ To 3.3 MHz Data Input Rate
■ Low Output-Saturation Voltages
■ Low-Power CMOS Logic and Latches
Always order by complete part number, e.g., UCN5812AF .
■ Active DMOS Pull-Downs
■ Reduced Supply Current
Requirements
■ Improved Replacement
for TL5812
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF
FUNCTIONAL BLOCK DIAGRAM
LOAD
SUPPLY
SERIAL
DATA OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BLANKING
GROUND
1
V
BB
2
326
20
4
19
5
18
6
17
7
16
BLNK
LATCHES
REGISTER
8
15
9
14
10
13
11
12
12
11
13
14 27
LATCHES
REGISTER
V
ST
CLK
DD
28
27
25
24
23
22
21
20
19
18
17
28
16
15
Dwg. PP-029-7
SUPPLY
SERIAL
DATA IN
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
OUT
9
OUT
10
STROBE
CLOCK
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
LOGIC
GROUND
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
OUT1OUT
OUT
2
3
OUT
V
MOS
BIPOLAR
V
N
LOGIC
DD
SUPPLY
SERIAL
DATA OUT
LOAD
BB
SUPPLY
Dwg. FP-013-1
TYPICAL INPUT CIRCUIT
V
DD
IN
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1988, 2000 Allegro MicroSystems, Inc.
V
BB
OUT
N
Dwg. No. A-14,219
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted).
Limits @ VDD = 5 V Limits @ VDD = 12 V
Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current I
Output Voltage V
Output Pull-Down Current I
Input Voltage V
Input Current I
Serial Data V
Maximum Clock Frequency f
Supply Current I
Blanking to Output Delay t
Output Fall Time t
Output Rise Time t
CEX
OUT(1)
V
OUT(0)
OUT(0)
IN(1)
V
IN(0)
IN(1)
I
IN(0)
OUT(1)
V
OUT(0)
clk
DD(1)
I
DD(0)
I
BB(1)
I
BB(0)
PHL
t
PLH
f
r
V
= 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA
OUT
I
= -25 mA, VBB = 60 V 58 58.5 — 58 58.5 — V
OUT
I
= 1 mA — 2.0 3.0 ——— V
OUT
I
= 2 mA ——— —2.0 3.5 V
OUT
V
= 5 V to V
OUT
V
= 20 V to V
OUT
BB
BB
2.0 3.5 — ——— mA
——— 8.0 13 — mA
3.5 — 5.3 10.5 — 12.3 V
-0.3 — +0.8 -0.3 — +0.8 V
VIN = V
DD
— 0.05 0.5 — 0.1 1.0 µA
VIN = 0.8 V — -0.05 -0.5 — -0.1 -1.0 µA
I
= -200 µA 4.5 4.7 — 11.7 11.8 — V
OUT
I
= 200 µA — 200 250 — 100 200 mV
OUT
3.3* —— ——— MHz
All Outputs High — 100 300 — 200 500 µA
All Outputs Low — 100 300 — 200 500 µA
Outputs High, No Load — 1.5 4.0 — 1.5 4.0 mA
Outputs Low — 10 100 — 10 100 µA
CL = 30 pF, 50% to 50% — 2000 ——1000 — ns
CL = 30 pF, 50% to 50% — 1000 ——850 — ns
CL = 30 pF, 90% to 10% — 1450 ——650 — ns
CL = 30 pF, 10% to 90% — 650 ——700 — ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
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