Allegro UCN5833EP, UCN5833A Datasheet
UCN5833EP
32
SERIAL DATA OUT
OUTPUT ENABLENCOUT
41
42
OE
LATCHES
19
20
OUT18OUT
OUT
Dwg. No. A-13,049
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
43
REGISTER
252627
17
. . . . . . . 7.0 V
+ 0.3 V
DD
D
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
31
30
29
28
27
26
25
24
23
22
21
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTNCSTROBE1POWER GROUND
6
2
7
3
8
4
9
5
10
6
11
7
12
13
8
14
9
15
10
11
16
17
12
18
NC
5
SERIAL DATA IN
2
3
4
ST
LATCHES
REGISTER
1920212223
15
13
14
16
OUT
OUT
OUT
OUT
LOGIC
SUPPLY
CLOCK
1
44
DD
V
CLK
SUB
24
OUT
LOGIC GROUND
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, V
Logic Supply Voltage, V
Input Voltage Range,
. . . . . . . . . -0.3 V to V
V
IN
Continuous Output Current,
(each output) . . . . . . . . . . 125 mA
l
OUT
Package Power Dissipation, P
(UCN5833A) . . . . . . . . . . . . . . . 3.5 W*
(UCN5833EP) . . . . . . . . . . . . . . 2.5 W*
Operating Temperature Range,
. . . . . . . . . . . . . . - 20°C to +85°C
T
A
Storage Temperature Range,
. . . . . . . . . . . . . -55°C to +150°C
T
S
* Derate linearly to 0 W at +150°C.
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
. . . . . . . . . . . 30 V
OUT
DD
5833
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVER
Designed to reduce logic supply current, chip size, and system
cost, the UCN5833A/EP integrated circuits offer high-speed operation
for thermal printers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak
output current rating. The combination of bipolar and MOS technologies gives BiMOS II smart power ICs an interface flexibility beyond the
reach of standard buffers and power driver circuits.
These 32-bit drivers have bipolar open-collector npn Darlington
outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS
shift register, and CMOS control circuitry. The high-speed CMOS shift
registers and latches allow operation with most microprocessor-based
systems at data input rates above 3.3 MHz. Use of these drivers with
TTL may require input pull-up resistors to ensure an input logic high.
The UCN5833A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. At an ambient temperature of
+75°C, all outputs of the DlP-packaged device will sustain 50 mA
continuously. For high-density applications, the UCN5833EP is
available. This 44-lead plastic chip carrier (quad pack) is intended
for surface-mounting on solder lands with 0.050" (1.27 mm) centers.
CMOS serial data outputs permit cascading for applications requiring
additional drive lines.
FEATURES
■ To 3.3 MHz Data Input Rate
■ 30 V Minimum Output Breakdown
■ Darlington Current-Sink Outputs
■ Low-Power CMOS Logic and Latches
Always order by complete part number:
Part Number Package
UCN5833A 40-Pin DIP
UCN5833EP 44-Lead PLCC
26185.16A*
Data Sheet
5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
UCN5833A
LOGIC
SUPPLY
SERIAL
DATA I N
POWER
GROUND
STROBE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
V
DD
2
3
4
ST
5
1
6
2
7
3
8
4
9
5
10
6
11
7
12
8
12
9
14
10
15
11
16
12
17
13
18
14
19
15
20
16
LATCHES
REGISTER
REGISTER
CLK
OE
LATCHES
SUB
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
LOGIC
CLOCK
SUPPLY
SERIAL
DATA O U T
OUTPUT
ENABLE
OUT
32
OUT
31
OUT
30
OUT
29
OUT
28
OUT
27
OUT
26
OUT
25
OUT
24
OUT
23
OUT
22
OUT
21
OUT
20
OUT
19
OUT
18
OUT
17
LOGIC
GROUND
CLOCK
SERIAL
DATA I N
STROBE
OUTPUT
ENABLE
FUNCTIONAL BLOCK DIAGRAM
32-BIT SHIFT REGISTER
LATCHES
OUT
OUT
OUT
1
3
2
POWER
GROUND
OUT
OUT OUT
30
32
31
TYPICAL INPUT CIRCUIT
V
DD
IN
V
DD
SERIAL DATA
OUT
LOGIC
GROUND
SUB
MOS
BIPOLAR
Dwg. No. A-13,057
Dwg. No. A-13,048
SUB
TYPICAL OUTPUT DRIVER
115 Northeast Cutoff, Box 15036
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1986, 1995, Allegro MicroSystems, Inc.
Dwg. No. A-13,050
OUT
Dwg. No. A-13,051
5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Max. Units
Output Leakage Current I
Collector-Emitter V
Saturation Voltage
Input Voltage V
Input Current l
Serial Output Voltage V
V
Supply Current l
CEX
CE(SAT)
IN(1)
V
IN(0)
IN(1)
l
IN(0)
OUT(1)
OUT(0)
DD
V
= 30 V, TA = 70°C—10µA
OUT
l
= 50 mA — 1.2 V
OUT
l
= 100 mA — 1.7 V
OUT
3.5 5.3 V
-0.3 +0.8 V
VIN = 5.0 V — 1.0 µA
VIN = 0 V — -1.0 µA
I
= -200 µA 4.5 — V
OUT
I
= 200 µA — 0.3 V
OUT
One output ON, l
= 100 mA — 1.0 mA
OUT
All outputs OFF — 50 µA
Output Rise Time t
Output Fall Time t
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
r
f
l
= 100 mA, 10% to 90% — 500 ns
OUT
l
= 100 mA, 90% to 10% — 500 ns
OUT
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Output Contents
Data Clock Data Strobe Enable
Input Input I
1I2I3
HHR
LLR
XR
1R2R3
XXX...X X X L R1R2R3... R
P1P2P3... P
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
1R2
1R2
... I
... R
... R
... R
N-1IN
N-2RN-1
N-2RN-1
N-1RN
N-1PN
Output Input I1I2I3... I
R
N-1
R
N-1
R
N
P
N
HP1P2P3... P
X X X ... X X L H H H ... H H
N-1IN
N-1 RN
N-1 PN
Input I1I2I3... I
HP1P2P3... P
N-1
N-1
I
P
N
N
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