5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
5832
Always order by complete part number:
Part Number Package
UCN5832A 40-Pin DIP
UCN5832EP 44-Lead PLCC
Intended originally to drive thermal printheads, the UCN5832A
and UCN5832EP have been optimized for low output-saturation
voltage, high-speed operation, and pin configurations most convenient
for the tight space requirements of high-resolution printheads. These
integrated circuits can also be used to drive multiplexed LED displays
or incandescent lamps at up to 150 mA peak current. The combination
of bipolar and MOS technologies gives BiMOS II arrays an interface
flexibility beyond the reach of standard buffers and power driver
circuits.
The devices each have 32 bipolar NPN open-collector saturated
drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS
shift registers, and CMOS control circuitry. The high-speed CMOS
shift registers and latches allow operation with most microprocessor
based systems. Use of these drivers with TTL may require input
pull-up resistors to ensure an input logic high. MOS serial data
outputs permit cascading for interface applications requiring additional
drive lines.
The UCN5832A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. Under normal operating conditions, this device will allow all outputs to sustain 100 mA continuously
without derating. The UCN5832EP is supplied in a 44-lead plastic
leaded chip carrier for minimum area, surface-mount applications.
Both devices are also available for operation from -40°C to +85°C.
To order, change the prefix from ‘UCN’ to ‘UCQ’.
Similar 32-bit serial-input latched source drivers are available as
the UCN5818AF/EPF. Other high-voltage, high-current 8-bit devices
are available as the UCN5821A, UCN5841A/LW, and UCN5842A.
FEATURES
■ To 3.3 MHz Data Input Rate
■ Low-Power CMOS Logic and Latches
■ 40 V Current Sink Outputs
■ Low Saturation Voltage
■ Automotive Capable
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
V
DD
SERIAL
DATA IN
GROUND
STROBE
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
6
OUT
7
OUT
8
OUT
9
OUT
10
OUT
11
OUT
12
OUT
13
OUT
14
OUT
18
OUT
19
OUT
20
OUT
21
OUT
22
OUT
23
OUT
24
OUT
25
OUT
26
OUT
27
OUT
28
OUT
29
OUT
30
OUT
31
OUT
32
OUTPUT
ENABLE
CLOCK
SERIAL
DATA OUT
INTERNAL
CONNECTION
LOGIC
SUPPLY
40
39
38
37
34
35
36
31
32
33
30
22
29
28
27
26
25
24
23
21
1
2
3
4
7
6
5
10
9
8
11
12
12
14
15
16
17
18
19
20
OUT
15
OUT
16
OUT
17
LATCHES
REGISTER
REGISTER
LATCHES
Dwg. No. A-12,377A
Data Sheet
26185.10B
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, V
OUT
......................40 V
Logic Supply Voltage, V
DD
................15 V
Input Voltage Range,
V
IN
...................-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
l
OUT
.................................. 150 mA
Package Power Dissipation,
P
D
................................ See Graph
Operating Temperature Range,
T
A
........................... -20°C to +85 °C
Storage Temperature Range,
T
S
..........................-55°C to +150°C
Caution: CMOS devices have input-static
protection but are susceptible to damage when
exposed to extremely high static electrical charges.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5832EP
FUNCTIONAL BLOCK DIAGRAM
Dwg. No. A-14,360
1
4
5
6
18
19
20
21
22
23
24
25
262728
40
41
42
43
44
2
3
7
8
9
10
11
12
13
14
15
16
17
OUTNCSTROBE1GROUND
SERIAL
DATA IN
LOGIC
SUPPLY
CLOCK
SERIAL
DATA OUT
OUTPUT
ENABLENCOUT
32
38
39
37
36
35
34
33
32
31
30
29
OUT
31
OUT
21
NC
OUT
13
OUT
16
IC
OUT
17
OUT
20
NC
V
DD
32
SHIFT REGISTER
LATCHES
SHIFT REGISTER
LATCHES
OUT
12
OUT
2
32-BIT SHIFT REGISTER
LATCHES
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
V
DD
SERIAL DATA
OUT
MOS
BIPOLAR
OUT
OUT
OUT
OUT
OUT OUT
1
2
3
30
31
32
GROUND
50 75 100 125 150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °C
2.0
1.5
1.0
25
Dwg. GP-025A
3.0
SUFFIX 'EP', R = 46°C/W
θJA
SUFFIX 'A', R = 36°C/W
θJA
Copyright © 1984, 1998, Allegro MicroSystems, Inc.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
DD
= 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Max. Units
Output Leakage Current I
CEX
V
OUT
= 40 V, TA = 70°C—10µA
Collector-Emitter V
CE(SAT)
l
OUT
= 50 mA — 275 mV
Saturation Voltage
l
OUT
= 100 mA, “A” package 150 550 mV
l
OUT
= 100 mA, “EP” package — 550 mV
Input Voltage V
IN(1)
3.5 5.3 V
V
IN(0)
-0.3 +0.8 V
Input Current l
IN(1)
VIN = 3.5 V — 1.0 µA
l
IN(0)
VIN = 0.8 V — -1.0 µA
Input lmpedance Z
IN
VIN = 3.5 V 3.5 — MΩ
Serial Data Output Resistance R
OUT
—20 kΩ
Supply Current l
DD
One output ON, l
OUT
= 100 mA — 5.0 mA
All outputs OFF — 50 µA
Output Rise Time t
r
l
OUT
= 100 mA, 10% to 90% — 1.0 µs
Output Fall Time t
f
l
OUT
= 100 mA, 90% to 10% — 1.0 µs
TYPICAL OUTPUT DRIVERTYPICAL INPUT CIRCUIT
IN
V
DD
Dwg. No. A-12,379A
Dwg. No. A-12,380A
OUT
V
DD
675Ω
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Serial Data present at the input is transferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel conversion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low,
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of the latches.
E F
CLOCK
DATA IN
STROBE
N
A D
B
C
G
OUTPUT
ENABLE
OUT
Dwg. No. A-12,276A
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Output Contents
Data Clock Data Strobe Enable
Input Input I
1I2I3
... I
N-1IN
Output Input I1I2I3... I
N-1IN
Input I1I2I3... I
N-1
I
N
HHR
1R2
... R
N-2RN-1
R
N-1
LLR
1R2
... R
N-2RN-1
R
N-1
XR
1R2R3
... R
N-1RN
R
N
XXX...X X X L R1R2R3... R
N-1 RN
P1P2P3... P
N-1PN
P
N
HP1P2P3... P
N-1 PN
HP1P2P3... P
N-1
P
N
X X X ... X X L H H H ... H H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time)..........................................................................75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ........................................................................... 500 ns
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
40
0.580
0.485
12
3
0.250
MAX
0.070
0.030
0.015
MIN
0.022
0.014
0.015
0.008
0.600
BSC
Dwg. MA-003-40 in
20
0.100
BSC
0.005
MIN
0.200
0.115
4
0.700
MAX
21
2.095
1.980
40
14.73
12.32
12
3
6.35
MAX
1.77
0.77
0.39
MIN
0.558
0.356
0.381
0.204
15.24
BSC
Dwg. MA-003-40 mm
20
2.54
BSC
0.13
MIN
5.08
2.93
4
17.78
MAX
21
53.2
50.3
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5832EP
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
18
28
Dwg. MA-005-44A in
0.020
MIN
0.050
BSC
144
0.021
0.013
INDEX AREA
2
6
7
17
29
39
40
0.695
0.685
0.032
0.026
0.319
0.291
0.319
0.291
0.180
0.165
0.695
0.685
0.656
0.650
0.656
0.650
Dwg. MA-005-44A mm
17.65
17.40
0.51
MIN
4.57
4.20
17.65
17.40
16.662
16.510
1.27
BSC
0.812
0.661
144
0.533
0.331
INDEX AREA
2
28
29
39
40
6
7
17
18
16.662
16.510
8.10
7.39
8.10
7.39
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.
BiMOS II (Series 5800) & DABiC IV (Series 6800)
INTELLIGENT POWER INTERFACE DRIVERS
SELECTION GUIDE
Function Output Ratings * Part Number †
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers) -120 mA 50 V‡ 5895
8-Bit 350 mA 50 V 5821
8-Bit 350 mA 80 V 5822
8-Bit 350 mA 50 V‡ 5841
8-Bit 350 mA 80 V‡ 5842
9-Bit 1.6 A 50 V 5829
10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10
12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811
20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812
32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818
32-Bit 100 mA 30 V 5833
32-Bit (saturated drivers) 100 mA 40 V 5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit 350 mA 50 V‡ 5800
8-Bit -25 mA 60 V 5815
8-Bit 350 mA 50 V‡ 5801
SPECIAL-PURPOSE FUNCTIONS
Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804
Addressable 28-Line Decoder/Driver 450 mA 30 V 6817
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
† Complete part number includes additional characters to indicate operating temperature range and package style.
‡ Internal transient-suppression diodes included for inductive-load protection.
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