Datasheet UCN5829EB Datasheet (Allegro)

C

EN

9

IN

RC

SUPPLY

RC

HIGH-SIDE

DRIVER

5

6

GND

7

8

ONE-SHOT

9

10

11

12

13

14

15

16

17 29

GND GND

NC

18

NO

CONNECTION

3

4

V

DD

19

21

20

9

8

7

OUT

OUT

OUT

SERIAL DATA

OUT

1

2

CLK

SHIFT REGISTER

LATCHES

23

22

5

6

OUT

OUT

CLOCK

44

24

4

OUT

SERIAL DATA

IN

STROBE

43

424140

25

26

3

2

OUT

OUT

CV

R

CURRENT
CONTROL

27

1

OUT

REFERENCE

NC

28

NO

CONNECTION

GND

39

38

37

36

35

34

33

32

31

30

Dwg. PP-028A

ABSOLUTE MAXIMUM RATINGS

Output Current Voltage, V
Output Current, I

OUT(S)

(Continuous) ................................ 1.6 A

(Peak)............................................ 1.8 A

Logic Supply Voltage, V
Input Voltage Range,

V

....................... -0.3 V to V

IN

Package Power Dissipation,

PD........................................ See Graph

Operating Temperature Range,

T

..................................-20°C to +85°C

A

Junction Temperature, T

DISCONTINUED PRODUCT

Storage Temperature Range,

............................... -55°C to +150°C

T

S

* Fault conditions that produce excessive junction
temperature will activate device thermal shut­down circuitry. These conditions can be
tolerated, but should be avoided.

Caution: This CMOS device has input static
protection but is susceptible to damage when
exposed to extremely high static electrical
charges.

—

............ 50 V

OUT

.................. 7.0 V

DD

+ 0.3 V

DD

............... +150°C*

J

FOR REFERENCE ONL

26185.50

5829

9-BIT SERIAL-INPUT,

LATCHED SINK DRIVER

Intended primarily to drive high-current, dot matrix 9- and 24-wire
printer solenoids, the UCN5829EB serial-input, latched sink driver
provides a complete driver function with a minimum external parts
count. Included on chip are constant-frequency PWM current control
for each output driver, a user-defined output enable timeout, current
sensing, and thermal shutdown.

The 9-bit CMOS shift register and latches allow operation with
most microprocessor/LSI-based systems. With a 5 V logic supply,
these BiMOS devices will operate at data input rates greater than 3.3
MHz. The CMOS inputs cause minimum loading and are compatible
with standard CMOS, PMOS, NMOS, and TTL circuits. A CMOS serial
data output allows cascade connections in applications requiring
additional drive lines as required for 24-wire printheads.

The device features nine open-collector Darlington drivers, each
rated at 50 V and 1.6 A. Current-control for each output is provided by
an internal current-sensing resistor and a constant-frequency chopper
circuit. An external high-side driver can be used to optimize print head
performance. It is enabled by an on-chip driver during the output
enable timeout. Internal logic sequencing prevents false output
operation during power up. Other high-current devices for driving dot
matrix printheads are the UDN2961B/W and UDN2962W.

The UCN5829EB is supplied in a 44-lead power PLCC. Its
batwing construction provides for maximum package power dissipation
in a minimum-area, surface-mountable package.

FEATURES

■ 1.6 A Continuous Output Current

■ 50 V Minimum Sustaining Voltage

■ Internal Current Sensing

■ Constant-Frequency PWM Current Control

■ Control for External High-Side Driver

■ To 3.3 MHz Data Input Rate

■ Low-Power CMOS Logic & Latches

■ Internal Pull-Ups for TTL Compatibility

■ User-Defined Output Enable Timeout

■ Internal Thermal Shutdown Circuitry

Y

Data Sheet

Always order by complete part number: UCN5829EB .

5829

9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER

FUNCTIONAL BLOCK DIAGRAM

R

EN

C

EN

STROBE

CLOCK

SERIAL

DATA IN

SERIAL

DATA OUT

IN

+5 V

3

V

DD

4

42

44

43

1

2

9

P.O.R.

ONE-SHOT

SHIFT REGISTER

LATCHES

7-17

29-39

HIGH-SIDE

DRIVER

65

TO DRIVERS 1, 3, 5, 7, 9

+5 V

÷2

CHOP INHIBIT

S RQ

TO DRIVERS 4, 6, 8

DRIVER TWO
OF NINE
DRIVERS

R

C

CURRENT

LEVEL

CONTROL

+
–

C

C

40

V

REF

41

R =
5 kΩ

±1%

OUT

26

2

<<1 Ω

Dwg. FP-015A

CV

12.5

R

θ

J

T

=

6

°

10

C

7.5

5.0

2.5

0

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

25

R

=

θJA

3

0

°C

/W

50 75 100 125 150

TEMPERATURE IN °C

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 1991, 1995 Allegro MicroSystems, Inc.

/W

Dwg. GP-020B

LATCHED SINK DRIVER

TYPICAL INPUT CIRCUITS TYPICAL OUTPUT DRIVER

V

DD

IN

Dwg. EP-010-3

ELECTRICAL CHARACTERISTICS at T
in Test Circuit/Typical Application (unless otherwise noted).

= +25°C, V

A

DD

= 5 V,

5829

9-BIT SERIAL-INPUT,

OUT

N

<<1 Ω

Dwg. EP-021-2

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Power Drivers (OUT

through OUT9) with V

1

Output Leakage Current I
Output Saturation Voltage V

OUT(SAT)

Output Sustaining Voltage V

OUT

OUT(sus)

REF

≥4.5 V

V

= 50 V — 1.0 100 µA

OUT

I

= 1.0 A — 1.0 1.5 V

OUT

I

= 1.6 A — 1.5 1.9 V

OUT

I

= 1.6 A, L = 2.5 mH 50 — — V

OUT

Control Logic
HSD Output Saturation Voltage V

CE(SAT)

Logic Input Voltage V

V

Logic Input Current I

Reference Input Current I
Logic Supply Current I

(V

= 2.0 V)

REF

Maximum Clock Frequency f
Serial Data Output Voltage V

OUT(1)

V

OUT(0)

Clock to Serial Data Out Delay t
Thermal Shutdown Temperature T

IN(1)
IN(0)

IN

REF

DD

clk

PD

J

IC = 20 mA — 0.5 1.0 V

3.5 — 5.3 V

-0.3 — 0.8 V
VIN = 5.0 V — — 1.0 µA
V

= 0.8 V — -90 -180 µA

IN

V

= 3.0 V — 500 900 µA

REF

All Drivers OFF — 15 25 mA
All Drivers ON, No Load — 55 75 mA

3.3 5.0 — MHz

I

= -200 µA 4.5 4.7 — V

OUT

I

= 200 µA — 250 — mV

OUT

C

= 30 pF — — 300 ns

L

— 165 — °C

Continued next page...

5829

9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER

ELECTRICAL CHARACTERISTICS at T

= +25°C, V

A

DD

= 5 V,

in Test Circuit/Typical Application (unless otherwise noted).

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Units
Chopping Characteristics (T

Enable Timeout t
Chopping Frequency f
Duty Cycle Range dc t
Chop Current Level I

Output Current Control Range V

Delay t
Chop Inhibit Voltage Range V

Negative current is defined as coming out of (sourcing) the specified device terminal.

= +25°C to +150°C) with Fast Clamp Diodes

J

EN

ch

TRIP

REF

I

TRIP

REF

d

REN = 20 kΩ, CEN = 0.01 µF 190 200 210 µs
RC = 20 kΩ, CC = 250 pF 90 100 110 kHz

/ ton + t

on

V

REF

V

REF

I

TRIP

off

= 2.0 V, fch < 100 kHz 0.9 1.0 1.1 A
= 2.8 V, fch < 100 kHz 1.26 1.4 1.54 A

to I

, TA = +25°C — 300 500 ns

OUT(P)

15 — < 50 %

1.0 — 3.2 V

0.5 — 1.6 A

4.5 — VDD + 0.3 V

V + 10 V

BB

Dwg. EP-027

EXTERNAL HIGH-SIDE DRIVERS

CHARGE-PUMP CIRCUITRY

FOR SINGLE-SUPPLY OPERATIONPMOSNMOS

V

V

BB

BB

0.022
µF

10 V

Dwg. EP-028

V

BB

Dwg. EP-026

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

CHARGE

PUMP

+36 V

LATCHED SINK DRIVER

TEST CIRCUIT AND

TYPICAL APPLICATION

POWER
NMOS

LOADS (9)

5829

9-BIT SERIAL-INPUT,

V

DD

V

REF

STROBE

CLOCK

SERIAL

DATA IN

OUTPUTS

HIGH-SIDE
DRIVER (HSD)

GROUND

5 kΩ ±1%

R

CV

RC

V

RC

IN

DD

EN

+

20 µF

C

250 pF

9

0.01
µF

20 kΩ

SERIAL
DATA OUT

Dwg. EP-023A

20 kΩ

TRUTH TABLE

Serial Shift Register Serial Latch Output
Data Clock Contents* Data Strobe Contents* Contents* HSD

Input Input I

HHR

LLR
XR

XX… XX HR1R2… R
P1P2… P

1I2

1R2

… I
… R

1

… R

1

… R

Output Input I1I2…I

9

R

8
8
9

9

7

R

7

R

8

P

8

HX H L

LP1P2… P

I1I2…I9OUTPUT

9

9

P1P2… P

9

9

H

* Serial Data Output connected to Input9.
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

5829

9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER

CLOCK

A

DATA IN

C

STROBE

D

B

E

F

G

HIGH-SIDE

DRIVER OUT

H

LOAD

CURRENT

t

on

TO I

I

OUT(asym)

OUT(P)

t

d

t

off

I

TRIP

Dwg. WP-011A

TIMING CONDITIONS

T

= +25°C, Logic Levels are V

A

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns

B. Minimum Data Active Time After Clock Pulse

C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ns

D. Minimum Clock Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ns

E. Minimum Time Between Clock Activation and Strobe. . . . . . . . . . . 500 ns

F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns

G. Enable Timeout, t
H. Chop Period*, ton + t

* Chopping is disabled if V

(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns

.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REN C

EN

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 RC C

off

is greater than 4.5 V.

REF

and Ground

DD

EN

C

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

5829

9-BIT SERIAL-INPUT,

LATCHED SINK DRIVER

APPLICATIONS INFORMATION

The UCN5829EB is designed to drive high-current, 9- or 24-wire
(3 devices cascaded) dot matrix impact printer solenoids. The internal
CMOS control logic:

1) selects the operating channels from a 9- or 24-bit word

previously loaded into the shift register,

2) controls the peak load current of the output drivers via nine

constant-frequency switch-mode current choppers,

3) sets a user-defined print enable time, and

4) turns ON an external high-side driver during the print enable

interval.

Data present at the SERIAL DATA INPUT is transferred to the shift
register on the low-to-high transition of the CLOCK input pulse. The
data must appear at the input prior to the rising edge of the clock input
waveform. On succeeding clock pulses, the registers shift data infor­mation towards the SERIAL DATA OUTPUT. Information present at
any register is transferred to its respective latch on the high-to-low
transition of the STROBE (serial-to-parallel conversion). Drivers that
have a logic high stored in their latch will be enabled for a set time
interval (tEN) generated by an internal one-shot. The output current is
internally sensed and controlled in a fixed-frequency chopper format.
Between strobe pulses, a new data word can be clocked in for the next
print enable cycle.

PRINT ENABLE TIME

A high-to-low transition of the STROBE input starts an internal
one-shot which sets the print enable time (tEN) of the output drivers and
the external high-side driver. The print enable time is determined by an
external resistor (50 kΩ max) and capacitor (100 pF min) at RCEN as

tEN=REN C

The print enable time can also be controlled from a microproces­sor. In this mode, the internal one-shot is operated as an output
disable function. In this mode, REN and CEN are not used; instead a
10 kΩ series resistor is connected between RCEN and an externally
generated output disable pulse. As before, on the high-to-low
STROBE transition, the outputs will be enabled. They will remain
enabled until a low-to-high logic (≥3.3 V) DISABLE transition at RCEN.

When operating in a continuous chopping mode, and neither print
enable timeout nor output disable are desired, RCEN should be
grounded.

EN

5829

9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER

HIGH-SIDE DRIVER

To reduce the current decay time at the end of a print enable
cycle, an external high-side driver can be used and controlled by the
HIGH-SIDE DRIVER (HSD) output. The HSD is designed to drive an
external N-channel MOSFET (with accompanying charge pump
circuitry). During the print enable time (t
driver is OFF, allowing the external high-side driver to be ON. If the
external high-side driver is a P-channel device (eliminating the need
for charge-pump circuitry), the HSD signal must be inverted for correct
operation.

If an external high-side driver is used, an external ground clamp

diode is also required.

OUTPUT CURRENT CONTROL

Each of the nine channels consists of a power Darlington sink
driver, internal low-value current-sensing resistor, comparator, and an
R/S flip-flop. The output current is sensed and controlled indepen­dently in each channel by means of a fixed-frequency chopper which
sets the flip-flop and allows the output to turn ON. As the current
increases in the load it is sensed by the internal sense resistor until the
sense voltage equals the trip voltage of the comparator. At this time,
the flip-flop is reset and the output is turned OFF. Over the range of
V

= 1.0 V to 3.2 V, the output current trip point is a linear function

REF

of the reference voltage:

), the internal high-side

EN

I

= V

C

REF

/2

TRIP

To ensure an accurate chop current level, an external 5 kΩ
resistor (RCV) is used. The actual load current peak will be slightly
higher than the trip point (especially for low-inductance loads) because
of the internal logic and switching delays (typically 300 ns). After turn­off, the load current decays, circulating through the load and an
external clamp diode. The output driver will stay OFF until the next
chop pulse sets the flip-flop, turning ON the output, and allowing load
current to rise again. The cycle repeats, maintaining the average
printhead current at the desired level.

The chop pulse frequency is determined by an external resistor
and capacitor at RCC:

fch=

To reduce the power supply and ground noise developed when
operating nine channels synchronously, the outputs are split into two
groups (OUTPUTS 2, 4, 6, 8 and OUTPUTS 1, 3, 5, 7, 9) for chopping
pulses.

1

2 RC C

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

5829

9-BIT SERIAL-INPUT,

LATCHED SINK DRIVER

The chopping function is disabled when V

operation at higher than allowable current levels, V

> 4.5 V. To prevent

REF

should not

REF

exceed 3.2 V, except to disable the chopping function.

DUTY CYCLE LIMITS

For correct operation of the UCN5829EB, the duty cycle must
be between 15% and 50% with 20% to 40% recommended. The lower
limit is due to internal lockout circuitry while the upper limit guarantees
synchronous operation. The duty cycle (dc) can be calculated as

t

on

I

OUT(P)

/ I

OUT(asym)

+ vd / v

c

≈dc =

where I

ton + t

off

OUT(asym)

= the asymptotic current value = vc/R
vd= discharge voltage across the load = V
vc= charge voltage across the load = VBB - V

1 + vd / v

c

L

+ V

HSD

DIODE

OUT(SAT)

- V

HSD

For most practical cases, correct operation can be achieved if
I

OUT(asym)

/ I

OUT(P)

> 2.5.

GENERAL

For applications with 9-wire printheads, SERIAL DATA OUT
should be connected to IN9. For 24-wire printhead applications, three
devices (eight channels per device) are cascaded by connecting
SERIAL DATA OUT to the next SERIAL DATA IN.

Each of the CMOS logic inputs have internal pull-up resistors for

TTL compatibility.

An external transient-protection flyback diode is required at each
output. Fast recovery diodes are recommended to reduce power
dissipation in the UCN5829EB. Internal filtering prevents false trigger­ing of the current sense comparator which can be caused by the
recovery current spike of the diodes when the outputs turn ON.

The SUPPLY terminal should be well decoupled with a capacitor
placed as close as possible to the device. Internal power-ON reset
circuitry prevents false output triggering during power up.

Thermal protection circuitry is activated and turns OFF all drivers
at a junction temperature of typically +165°C. The thermal shutdown is
independent of all other functions. It should not be used as another
control input but is intended only to protect the chip from catastrophic
failures due to excessive junction temperatures. The output drivers are
re-enabled when the junction temperature cools down to approximately
+145°C.

5829

9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER

TYPICAL APPLICATION

Shown is a typical application with the UCN5829EB controlling
a chop current of 1 A through a 3 mH, 9 Ω load. To check the duty
cycle and I

OUT(asym)/IOUT(P)

restrictions

where vd=V

vc=VBB - V
I

OUT(asym)

then I

OUT(asym)

The condition of I

HSD

+ V

OUT(SAT)

≈ 1.5 + 1.5 = 3

DIODE

- V

HSD

=vc / RL= 33 / 9 = 3.67

/ I

OUT(asym)

= 3.67 / 1 = 3.67

OUT(P)

/ I

OUT(P)

> 2.5 is met and the duty cycle will

= 36 - 1.5 - 1.5 = 33

be within the proscribed limits. The actual duty cycle is

I

dc = = = 32%

OUT(P) /IOUT(asym)

1 + vd/v

+ vd/v

c

1.0/3.67 + 2.5/33

c

1 + 2.5/33

For a 50 kHz chopping frequency and a 250 µs print enable time, the
remaining component values are

with CC= 250 pF and CEN= 0.01 µF
then RC= 1/(2 fch CC) = 1/(2 x 50 x 103 x 250 x 10
and REN= t

/ CEN= 250 x 10-6 / 10 x 10-9= 25 kΩ

EN

-12

) = 40 kΩ

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Dimensions in Inches

(controlling dimensions)

5829

9-BIT SERIAL-INPUT,

LATCHED SINK DRIVER

0.319

0.291

0.319

0.291

0.021

0.013

0.050

BSC

0.695

0.685

0.656

0.650

0.032

0.026

29

39

28

40

18

17

INDEX AREA

7

144

2

6

0.020

MIN

0.180

0.165

NOTES: 1. Webbed lead frame. Leads 7 through 17 and 29 through 39 are internally one piece.

2. Exact body and lead configuration at vendor’s option within limits shown.

3. Lead spacing tolerance is non-cumulative.

0.656

0.650

0.695

0.685

Dwg. MA-005-44A in

5829

9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER

Dimensions in Millimeters

(for reference only)

8.10

7.39

8.10

7.39

0.533

0.331

1.27

BSC

17.65

17.40

16.662

16.510

0.812

0.661

29

39

28

40

18

17

INDEX AREA

7

144

2

6

0.51

MIN

4.57

4.20

NOTES: 1. Webbed lead frame. Leads 7 through 17 and 29

through 39 are internally one piece.

2. Exact body and lead configuration at vendor’s
option within limits shown.

3. Lead spacing tolerance is non-cumulative.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

16.662

16.510

17.65

17.40

Dwg. MA-005-44A mm

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi­bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.