Datasheet UCN5811A Datasheet (Allegro)

OUT

OUT

BLANKING

SERIAL

DATA OUT

SERIAL

DATA IN

LOGIC

SUPPLY

CLOCK

STROBE

OUT

OUT

Data Sheet

26182.20B

5811

BiMOS II 12-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

Designed primarily for use with vacuum-fluorescent displays, the
UCN5811A smart power BiMOS II driver features low-output saturation
voltages and high output switching speed. These devices contain CMOS shift

1

11

2

12

BLNK

3

4

5

V

6

DD

7

CLK

8

ST

9

1

10

2

LATCHES

REGISTER

20

OUT

10

19

OUT

9

18

OUT

8

17

OUT

7

LOAD

16

V

BB

SUPPLY

GROUND

15

14

OUT

6

13

OUT

5

OUT

12

11

OUT

4

3

registers, data latches, and control circuitry, and bipolar high-speed sourcing
outputs with DMOS active pull-down circuitry. The high-speed shift register
and data latches allow direct interface with microprocessor-based systems. A
CMOS serial data output enables cascade connections in applications requir­ing additional drive lines.

The UCN5811A features 60 V and -40 mA output ratings, allowing it to
be used in many other peripheral power driver applications. It can be used as
an improved replacement tor the SN75512B. The Allegro devices do not
require special power-up sequencing.

The UCN5811A has been designed with BiMOS II logic for improved
data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At
12 V, higher speeds are possible. Use of this device with TTL may require
the use of appropriate pull-up resistors to ensure a proper input logic high.

Dwg. PP-029-5

ABSOLUTE MAXIMUM RATINGS

at

TA = 25°C

Logic Supply Voltage,VDD..................... 15 V

Driver Supply Voltage, VBB................... 60 V

Continuous Output Current,

......................... -40 mA to +25 mA

I

OUT

Input Voltage Range,

VIN....................... -0.3 V to VDD + 0.3 V

Package Power Dissipation,

........................................ See Graph

P

D

Operating Temperature Range,

................................. -20°C to +85°C

T

A

Storage Temperature Range,

TS............................... -55°C to +150°C

This device is supplied in a 20-pin plastic dual in-line package. It can be
operated over the ambient temperature range of -20°C to +85°C. Copper lead
frames and low output saturation voltages allow all outputs to be operated at
25 mA continuously at ambient temperatures of up to 76°C.

FEATURES

■ To 3.3 MHz Data Input Rate

■ Low-Power CMOS Logic and Latches

■ High-Speed Source Drivers

■ Active Pull-Downs

■ Low-Output Saturation Voltages

■ Improved Replacement for SN75512B

Always order by complete part number: UCN5811A .

5811

BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS

2.5

2.0

1.5

1.0

0.5

0

25

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

R = 55

θJA

°C/W

Dwg. GS-004-1

TYPICAL INPUT CIRCUIT

V

DD

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

FUNCTIONAL BLOCK DIAGRAM

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

GROUND

OUT1OUT

OUT

2

3

OUT

V

MOS

BIPOLAR

V

N

LOGIC

DD

SUPPLY

SERIAL
DATA OUT

LOAD

BB

SUPPLY

Dwg. FP-013-1

IN

Dwg. EP-010-5

TYPICAL OUTPUT DRIVER

Dwg. W-182

TIMING WAVESHAPES

Dwg. W-184

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 1985, 2000 Allegro MicroSystems, Inc.

5811

BiMOS II 12-BIT

SERIAL-INPUT,

LATCHED SOURCE DRIVERS

ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted).

Limits @ VDD = 5 V Limits @ VDD = 12 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

V

Output Leakage Current I

Output Voltage V

CEX

OUT(H)

V

OUT(L)

= 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA

OUT

I

= -25 mA, VBB = 60 V 58 58.5 — 58 58.5 — V

OUT

I

= 1 mA — 2.0 3.0 — — — V

OUT

= 2 mA — — — — 2.0 3.0 V

I

OUT

Output Pull-Down Current I

Input Voltage V

Input Current I

Serial Data Output Voltage V

Maximum Clock Frequency f

Supply Current I

Blanking to Output Delay t

Output Fall Time t

OUT(L)

IN(1)

V

IN(0)

IN(1)

I

IN(0)

OUT(H)

V

OUT(L)

clk

DD(H)

I

DD(L)

I

BB(H)

I

BB(L)

PHL

t

PLH

f

V

= 10 V to V

OUT

= 40 V to V

V

OUT

BB

BB

2.5 4.0 — — — — mA

— — — 15 18 — mA

3.5 — 5.3 10.5 — 12.3 V

-0.3 — +0.8 -0.3 — +0.8 V

VIN = V

DD

— 0.05 0.5 — 0.1 1.0 µA

VIN = 0.8 V — -0.05 -0.5 — -1.0 -1.0 µA

I

= -200 µA 4.5 4.7 — 11.7 11.8 — V

OUT

I

= 200 µA — 200 250 — 100 200 mV

OUT

3.3* — — — — — MHz

All Outputs High — 3.0 5.0 — 15 20 mA

All Outputs Low — 2.5 4.0 — 7.0 10 mA

Outputs High, No Load — 7.5 12 — 7.5 12 mA

Outputs Low — 10 100 — 10 100 µA

CL = 30 pF — 300 550 — 125 150 ns

CL = 30 pF — 250 450 — 170 200 ns

CL = 30 pF — 1000 1250 — 250 300 ns

Output Rise Time t

r

CL = 30 pF — 150 170 — 150 170 ns

Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

www.allegromicro.com

5811

BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS

CLOCK

A D

B

DATA IN

E F

C

STROBE

BLANKING

G

OUT

N

Dwg. No. 12,649A

TIMING REQUIREMENTS

(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) .......................................................................... 75 ns

B. Minimum Data Active Time After Clock Pulse

(Data Hold Time) ............................................................................. 75 ns

C. Minimum Data Pulse Width ................................................................ 150 ns

D. Minimum Clock Pulse Width ............................................................... 150 ns

E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns

F. Minimum Strobe Pulse Width ............................................................. 100 ns

G. Typical Time Between Strobe Activation and

Output Transistion ......................................................................... 500 ns

Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.

Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT­PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.

Information present at any register is trans­ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.

When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I

HHR

LLR

XR

P

N

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

1I2I3

1R2R3

XXX...X X X L R1R2R3... R

P1P2P3... P

1R2

1R2

... I

... R

... R

... R

N-1IN

N-2RN-1

N-2RN-1

N-1RN

N-1PN

Output Input I1I2I3... I

R

N-1

R

N-1

R

N

P

N

HP1P2P3... P

X X X ... X X H L L L ... L L

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

N-1IN

N-1 RN

N-1 PN

Blanklng I1I2I3... I

LP1P2P3... P

N-1

N-1

I

N

0.280

0.240

20

LATCHED SOURCE DRIVERS

UCN5811A

Dimensions in Inches

(controlling dimensions)

11

5811

BiMOS II 12-BIT

SERIAL-INPUT,

0.014

0.008

0.430

MAX

0.300

BSC

1

0.070

0.045

0.210

MAX

0.015

MIN

0.022

0.014

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

4. Supplied in standard sticks/tubes of 18 devices.

1.060

0.980

0.100

BSC

10

0.005

0.150

0.115

MIN

Dwg. MA-001-20 in

www.allegromicro.com

5811

BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS

Dimensions in Millimeters

20

7.11

6.10

UCN5811A

(for reference only)

11

0.355

0.204

7.62

BSC

10.92

MAX

10

5.33

MAX

0.39

MIN

1

1.77

1.15

0.558

0.356

26.92

24.89

2.54

BSC

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

4. Supplied in standard sticks/tubes of 18 devices.

3.81

2.93

0.13

MIN

Dwg. MA-001-20 mm

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

5811

BiMOS II 12-BIT

SERIAL-INPUT,

LATCHED SOURCE DRIVERS

www.allegromicro.com

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi­bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

5811

BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS

POWER

INTERFACE DRIVERS

Function Output Ratings* Part Number

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers) -120 mA 50 V‡ 5895
8-Bit 350 mA 50 V 5821
8-Bit 350 mA 80 V 5822
8-Bit 350 mA 50 V‡ 5841
8-Bit 350 mA 80 V‡ 5842
8-Bit (constant-current LED driver) 75 mA 17 V 6275
8-Bit (DMOS drivers) 250 mA 50 V 6595
8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595
8-Bit (DMOS drivers) 100 mA 50 V 6B595

10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10

12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811

16-Bit (constant-current LED driver) 75 mA 17 V 6276

20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812

32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818
32-Bit 100 mA 30 V 5833
32-Bit (saturated drivers) 100 mA 40 V 5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit 350 mA 50 V‡ 5800

†

8-Bit -25 mA 60 V 5815
8-Bit 350 mA 50 V‡ 5801
8-Bit (DMOS drivers) 100 mA 50 V 6B273
8-Bit (DMOS drivers) 250 mA 50 V 6273

SPECIAL-PURPOSE DEVICES

Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804
Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259
Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259
Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259
Addressable 28-Line Decoder/Driver 450 mA 30 V 6817

* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.

Negative current is defined as coming out of (sourcing) the output.

† Complete part number includes additional characters to indicate operating temperature range and package style.

‡ Internal transient-suppression diodes included for inductive-load protection.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]