Allegro TFA87(I), TFA87S, TFA88(I), TFA88S Schematic [ru]
TFA8x Series
Reverse Blocking T riode Thyristor
Features and Benefits
▪ Exceptional reliability
▪ Small fully-molded SIP package with heatsink mounting
for high thermal dissipation and long life
▪ Operating junction temperature to 150°C
▪ V
of 700 or 800 V
DRM
▪ 8.0 A
▪ 7 mA typical gate trigger current
▪ Uniform switching
▪ UL Recognized Component (File No.: E118037) (suffix I)
on-state current
RMS
Package: 3-pin SIP (TO-220F)
Description
This Sanken reverse blocking triode thyristor is designed for
AC power control, providing reliable, uniform switching for
half-cycle AC applications.
In comparison with other products on the market, the TFA8x
series provides increased isolation voltage (1800 VAC
guaranteed for up to 1 minute. In addition, commutation
dv/dt is improved.
RMS
),
Applications
▪ Motor control for small tools
▪ Temperature control, light dimmers, electric blankets
▪ General use switching mode power supplies (SMPS)
Not to scale
Typical Applications
M
Single-phase motor control (for example, electric tool) In-rush current control (for example, SMPS)
28105.03, Rev. 1
TFA8x
Reverse Blocking T riode Thyristor
Series
Selection Guide
V
Part Number
TFA87(I) 700 Yes
TFA87S 700 –
TFA88(I) 800 Yes
TFA88S 800 –
DRM
(V)
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Peak Repetitive Off-State Voltage V
Isolation Voltage V
Average On-State Current I
RMS On-State Current I
Surge On-State Current I
I2t Value for Fusing I2t Value for 50 Hz half cycle sine wave, 1 cycle, I
Critical Rising Rate of On-State Current di/dt
Peak Forward Gate Current I
Peak Forward Gate Voltage V
Peak Reverse Gate Current V
Peak Gate Power Dissipation P
Average Gate Power Dissipation P
Junction Temperature T
Storage Temperature T
DRM
T(AV)
T(RMS)
TSM
FGM
FGM
RGM
GM(AV)
UL-Recognized
ISO
GM
J
stg
Component
TFA87x
TJ = –40°C to 150°C, R
TFA88x
AC RMS applied for 1 minute between lead and case 1800 V
50 Hz half cycle sine wave, Conduction angle (α) = 180°,
continuous operation, TC = 98°C
f = 60 Hz
f = 50 Hz 120 A
I
= I
T
T(RMS)
ns, igp 30 mA (refer to Gate Trigger Circuit diagram)
f 50 Hz, duty cycle 10% 2.0 A
f 50 Hz, duty cycle 10% 10 V
f 50 Hz 5.0 V
f 50 Hz, duty cycle 10% 5.0 W
TJ < TJ(max) 0.5 W
Half cycle sine wave, single, non-repetitive
× π, VD = V
× 0.5, f ≤ 60 Hz, tgw 10 s, tgr ≤ 250
DRM
Package Packing
3-pin fully molded SIP with
heatsink mount
GREF
50 pieces per tube
= 1 k
= 120 A 72 A2 • s
TSM
700 V
800 V
12.6 A
132 A
–40 to 150 ºC
–40 to 150 ºC
8.0 A
50 A/s
Thermal Characteristics May require derating at maximum conditions
Characteristic Symbol Test Conditions Value Units
Package Thermal Resistance
(Junction to Case)
R
θJC
For AC 3.5 ºC/W
Pin-out Diagram
A
Number Name Function
G
K
123
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
1K
2 A Anode terminal
3 G Gate control
All performance characteristics given are typical values for circuit or
system baseline design only and are at the nominal operating voltage and
an ambient temperature, T
Cathode terminal
, of 25°C, unless oth er wise stated.
A
2
TFA8x
Reverse Blocking T riode Thyristor
Series
ELECTRICAL CHARACTERISTICS
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Off-State Leakage Current I
Reverse Leakage Current I
On-State Voltage V
Gate Trigger Voltage V
Gate Trigger Current I
Gate Non-trigger Voltage V
Holding Current I
Critical Rising Rate of
Off-State Voltage
DRM
RRM
dv/dt
VD = V
VD = V
I
TM
TM
VD = 6 V, RL = 10 , TC = 25°C – – 1.0 V
GT
VD = 6 V, RL = 10 , TC = 25°C – 7 15 mA
GT
VD = V
GD
R
H
GREF
VD = V
C
GREF
, TJ = 150°C, R
DRM
, TJ = 150°C, R
DRM
= 20 A, TC = 25°C – – 1.4 V
× 0.5, R
DRM
= 1 k, TJ = 25°C – 20 – mA
DRM
= 0.033 F
GREF
× 0.5, TJ = 125°C, R
= 1 k – – 2.0 mA
GREF
= 1 k – – 2.0 mA
GREF
= 1 k, TJ = 125°C 0.2 – – V
= 1 k,
GREF
– 300 – V/s
Test Circuit 1 Voltage-Current Characteristic
I
F
I
TM
R
GREF
C
GREF
Gate Trigger Current
t
gr
i
gp
t
gw
A
G
K
V
R
I
RRM
V
RRM
I
H
I
R
V
TM
(On state)
(Off state)
V
TM
V
DRM
I
DRM
V
F
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
TFA8x
Series
Reverse Blocking T riode Thyristor
Commutation Timing Diagrams
Q
4
Supply VAC
V
GATE
On-State
Currrent
A
V
GT
I
TSM
Q
A = Conduction angle
Q
Q
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
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