Allegro STR84145, STR83145 Datasheet

STR83145
STR84145

AND

Data Sheet

28190

INTERIM ISSUE

(subject to change without notice)

August 16, 1994

LATCH

+

2

MT1

3

MT2

4

GATE

1

DELAY

ABSOLUTE MAXIMUM RATINGS

OSC.

5

COMMON

Dwg. PK-005

LATCHED, UNIVERSAL

INPUT-VOLTAGE SWITCHES

Intended for power supplies with universal inputs (85 V to 265 V
rms), the STR83145 and STR84145 latched, universal input-voltage
switches incorporate timing, control, and drive circuitry with a high­current triac (bidirectional triode thyristor) switch. Each device senses
the applied ac line potential and automatically switches the rectifier and
associated capacitors between a voltage-doubler configuration (for line
voltages to 141 V) and a full-bridge configuration (for line voltages
greater than 149 V). This eliminates the possibility of user error with
adjustable jumpers or switches. Also, the related switch-mode power
stage need operate only over a reduced range of dc input voltages
when compared with "wide input" power supplies using a bridge rectifier
only. The reduction in dc input voltage range permits the use of lower­voltage capacitors and leads to a reduction in power stage stresses and
power dissipation. The STR83145 and STR84145 differ only in their
maximum ac current rating (10 A and 12 A, respectively).

The internal sensitive-gate triac is switched by a temperature­compensated constant-current gate driver driven by a 15 kHz pulse
train to reduce power dissipation. The switch-over voltage is accurately
set during manufacture for consistent operation. An user-adjustable
delay is provided to ensure start-up in the full-bridge mode. Once
established (by an input voltage greater than 149 V rms), an integral
latch holds the full-bridge mode to preclude false application of the
doubler mode during brownouts, voltage droops, or missing cycles.

The requirements of low transient thermal impedance and steady­state thermal resistance are satisfied in a molded, 5-lead single in-line
power package. Similar input-voltage switches, with a switch point of
159 V rms, are also available.

Repetitive Peak OFF-State Voltage,

V

............................................. 500 V

DRM

Static ON-State Current, I

STR83145...................................... 10 A

STR84145...................................... 12 A

Non-Repetitive Surge ON-State Current, I

STR83145.................................... 100 A

STR84145.................................... 120 A

Package Power Dissipation,

PD........................................ See Graph

Triac Junction Temperature, TJ..... +125°C

Frame Temperature, TM................ +100°C

Operating Temperature Range,

TA............................... -20°C to +125°C

Storage Temperature Range,

T

............................. -40°C to +125°C

stg

T(RMS)

TSM

FEATURES

■ Low Duty Cycle Triac Drive for Minimum Dissipation

■ For Universal Input Operation Between 85 V rms and 265 V rms

to 10 A or 12 A

■ Internal Latch Prevents False Mode Switching

■ Internal Sensitive-Gate Power Triac

■ Adjustable Start-Up Delay

■ Accurate 145 V rms Switch-Point Voltage

■ Low External Parts Count

■ Low Power Dissipation

■ Low-Power External Parts

Always order by complete part number:

Part Number Max. On-State Current
STR83145 10 A rms
STR84145 12 A rms

™

STR83145

3

512

4

AND

STR84145

LATCHED, UNIVERSAL
INPUT-VOLTAGE SWITCHES

FUNCTIONAL BLOCK DIAGRAM

GATE

MT1

DELAY

COMMON

REG.

+

7 V

MT2

LATCH

+

+

OSC.

Dwg. FK-004

ALLOWABLE PACKAGE POWER DISSIPATION

30

27 W

25

20

15

10

5

2 W

ALLOWABLE PACKAGE POWER DISSIPATION in WATTS

0

20 60 100

FREE AIR

40

150 mm x 150 mm x 2 mm

(WITH MICA SHEET)

100 mm x 100 mm x 2 mm

(WITH MICA SHEET)

75 mm x 75 mm x 2 mm

(WITH MICA SHEET)

TEMPERATURE in °C

P IS LIMITED BY T

DM

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Copyright © 1994 Allegro MicroSystems, Inc.

P IS LIMITED BY T

80 1200

INFINITE HEAT SINK

(NO MICA SHEET)

D

J

Dwg. GK-010

™

STR83145

AND

STR84145

LATCHED, UNIVERSAL
INPUT-VOLTAGE SWITCHES

SIMPLIFIED OPERATION

240–373 V peak

+

85–132 V rms

+

Voltage-Doubler Mode

ELECTRICAL CHARACTERISTICS

174–265 V rms

Full-Bridge Mode

at TA = +25°C, voltage measurements are referenced to Common (pin 3)

246–373 V peak

+

+

Dwg. EK-006

(unless otherwise noted).

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Units

On-State Voltage V

TM

STR83145, IT = 10 A* – – 1.8 V
STR84145, IT = 12 A* – 1.6 – V

Off-State Current I

DRM

STR83145, VD = 500 V – – 100 µA

STR84145, VD = 500 V – 40 – µA
Starting Voltage V
Startup Time Delay t
DC Switch-Over Voltage V

S

D

C

VT = 2 V – – 100 V

C2 = 1 µF, V

V

≤ 1 V 200 205 210 V

DELAY

≥ 100 V dc 40 – 100 ms

MT1

Temperature Coefficient
of Switch-Over Voltage α

Input Current I

Delay Terminal Voltage V

DELAY

Triac Gate-Drive Osc. Freq. f
Latch Reset Voltage V
Thermal Resistance R

VC

MT1

o

R

θJM

-20°C ≤ TM ≤ +100°C–±45 – mV/°C

Voltage-doubler mode, V

Full-bridge mode, V

V

ref. MT1, V

gate

V

= 400 mV 2.0 – 15 V

GATE

MT1

= 100 V – 15 – kHz

MT1

= 195 V – – 10 mA

MT1

= 400 V – – 6.5 mA

FET channel to mounting surface – – 1.8 °C/W
NOTES: Negative current is defined as coming out of (sourcing) the specified device terminal.

Typical Data is for design information only.
*In practical use, IT is recommended derated to 70%.

– – 7.0 V