Fully Integrated, Hall Effect-Based Linear Current Sensor IC
with 2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Features and Benefits
Low-noise analog signal path
Device bandwidth is set via the new FILTER pin
5 s output rise time in response to step input current
80 kHz bandwidth
Total output error 1.5% at TA = 25°C
Small footprint, low-profile SOIC8 package
1.2 m internal conductor resistance
2.1 kVRMS minimum isolation voltage from pins 1-4 to pins 5-8
5.0 V, single supply operation
66 to 185 mV/A output sensitivity
Output voltage proportional to AC or DC currents
Factory-trimmed for accuracy
Extremely stable output offset voltage
Nearly zero magnetic hysteresis
Ratiometric output from supply voltage
TÜV America
Certificate Number:
U8V 06 05 54214 010
Package: 8 Lead SOIC (suffix LC)
Description
The Allegro™ ACS712 provides economical and precise
solutions for AC or DC current sensing in industrial, commercial,
and communications systems. The device package allows for
easy implementation by the customer. Typical applications
include motor control, load detection and management, switchmode power supplies, and overcurrent fault protection. The
device is not intended for automotive applications.
The device consists of a precise, low-offset, linear Hall circuit
with a copper conduction path located near the surface of the
die. Applied current flowing through this copper conduction
path generates a magnetic field which the Hall IC converts into a
proportional voltage. Device accuracy is optimized through the
close proximity of the magnetic signal to the Hall transducer.
A precise, proportional voltage is provided by the low-offset,
chopper-stabilized BiCMOS Hall IC, which is programmed
for accuracy after packaging.
The output of the device has a positive slope (>V
when an increasing current flows through the primary copper
conduction path (from pins 1 and 2, to pins 3 and 4), which is
the path used for current sampling. The internal resistance of
this conductive path is 1.2 m typical, providing low power
loss. The thickness of the copper conductor allows survival of
IOUT(Q)
)
Approximate Scale 1:1
Continued on the next page…
Typical Application
1
IP+
2
IP+
I
Application 1. The ACS712 outputs an analog signal, V
that varies linearly with the uni- or bi-directional AC or DC
primary sampled current, IP , within the range specified. CF
is recommended for noise management, with values that
depend on the application.
ACS712
P
3
FILTER
IP–
4
IP–
VCC
VIOUT
GND
8
7
6
5
V
C
1 nF
OUT
+5 V
C
BYP
0.1 μF
F
OUT
.
ACS712-DS, Rev. 15
ACS712
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Description (continued)
the device at up to 5× overcurrent conditions. The terminals of the
conductive path are electrically isolated from the signal leads (pins
5 through 8). This allows the ACS712 to be used in applications
requiring electrical isolation without the use of opto-isolators or
other costly isolation techniques.
The ACS712 is provided in a small, surface mount SOIC8 package.
The leadframe is plated with 100% matte tin, which is compatible
with standard lead (Pb) free printed circuit board assembly processes.
Internally, the device is Pb-free, except for flip-chip high-temperature
Pb-based solder balls, currently exempt from RoHS. The device is
fully calibrated prior to shipment from the factory.
Selection Guide
Part NumberPacking*
ACS712ELCTR-05B-TTape and reel, 3000 pieces/reel–40 to 85±5185
ACS712ELCTR-20A-TTape and reel, 3000 pieces/reel–40 to 85±20100
ACS712ELCTR-30A-TTape and reel, 3000 pieces/reel–40 to 85±3066
*Contact Allegro for additional packing options.
TA
(°C)
Optimized Range, I
(A)
Sensitivity, Sens
P
(Typ) (mV/A)
Absolute Maximum Ratings
CharacteristicSymbolNotesRatingUnits
Supply Voltage V
Reverse Supply VoltageV
Output VoltageV
Reverse Output VoltageV
Output Current Source I
Output Current Sink I
Overcurrent Transient ToleranceI
Nominal Operating Ambient TemperatureT
Maximum Junction TemperatureTJ(max)165ºC
Storage TemperatureT
CC
RCC
IOUT
RIOUT
IOUT(Source)
IOUT(Sink)
P
A
stg
1 pulse, 100 ms100A
Range E–40 to 85ºC
8V
–0.1V
8V
–0.1V
3mA
10mA
–65 to 170ºC
Isolation Characteristics
CharacteristicSymbolNotesRatingUnit
Dielectric Strength Test Voltage*V
Working Voltage for Basic IsolationV
Working Voltage for Reinforced IsolationV
* Allegro does not conduct 60-second testing. It is done only during the UL certification process.
ISO
WFSI
WFRI
Agency type-tested for 60 seconds per
UL standard 60950-1, 1st Edition
For basic (single) isolation per UL standard
60950-1, 1st Edition
For reinforced (double) isolation per UL standard
60950-1, 1st Edition
Additional thermal information is available on the Allegro website.
2
The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connect-
2
R
Mounted on the Allegro ASEK 712 evaluation board5°C/W
JL
Mounted on the Allegro 85-0322 evaluation board, includes the power con-
JA
sumed by the board
23°C/W
ing the layers. Performance values include the power consumed by the PCB. Further details on the board are available from the Frequently Asked
Questions document on our website. Further information about board design and thermal performance also can be found in the Applications Information section of this datasheet.
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
ACS712
Definitions of Accuracy Characteristics
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Sensitivity (Sens). The change in device output in response to a
1 A change through the primary conductor. The sensitivity is the
product of the magnetic circuit sensitivity (G / A) and the linear
IC amplifier gain (mV/G). The linear IC amplifier gain is programmed at the factory to optimize the sensitivity (mV/A) for the
full-scale current of the device.
Noise (V
). The product of the linear IC amplifier gain
NOISE
(mV/G) and the noise floor for the Allegro Hall effect linear IC
(1 G). The noise floor is derived from the thermal and shot
noise observed in Hall elements. Dividing the noise (mV) by the
sensitivity (mV/A) provides the smallest current that the device is
able to resolve.
Linearity (E
). The degree to which the voltage output from
LIN
the IC varies in direct proportion to the primary current through
its full-scale amplitude. Nonlinearity in the output can be attributed to the saturation of the flux concentrator approaching the
full-scale current. The following equation is used to derive the
linearity:
100
where V
Δ gain × % sat (
1–
[{
2 (V
IOUT_half-scale amperes
IOUT_full-scale amperes
V
IOUT_full-scale amperes
= the output voltage (V) when the
– V
– V
IOUT(Q)
IOUT(Q)
)
)
[{
sampled current approximates full-scale ±IP .
Symmetry (E
). The degree to which the absolute voltage
SYM
output from the IC varies in proportion to either a positive or
negative full-scale primary current. The following formula is
used to derive symmetry:
V
IOUT_+ full-scale amperes
100
V
IOUT(Q)
– V
IOUT_–full-scale amperes
Quiescent output voltage (V
IOUT(Q)
– V
IOUT(Q)
). The output of the device
when the primary current is zero. For a unipolar supply voltage,
it nominally remains at VCC ⁄ 2. Thus, VCC = 5 V translates into
V
= 2.5 V. Variation in V
IOUT(Q)
IOUT(Q)
can be attributed to the
resolution of the Allegro linear IC quiescent voltage trim and
thermal drift.
Electrical offset voltage (VOE). The deviation of the device output from its ideal quiescent value of VCC / 2 due to nonmagnetic
causes. To convert this voltage to amperes, divide by the device
sensitivity, Sens.
Accuracy is divided into four areas:
0 A at 25°C. Accuracy at the zero current flow at 25°C, with-
out the effects of temperature.
0 A over Δ temperature. Accuracy at the zero current flow
including temperature effects.
Full-scale current at 25°C. Accuracy at the the full-scale current
at 25°C, without the effects of temperature.
Full-scale current over Δ temperature. Accuracy at the full-
scale current flow including temperature effects.
Ratiometry. The ratiometric feature means that its 0 A output,
V
proportional to its supply voltage, V
, (nominally equal to VCC/2) and sensitivity, Sens, are
IOUT(Q)
. The following formula is
CC
used to derive the ratiometric change in 0 A output voltage,
V
IOUT(Q)RAT
The ratiometric change in sensitivity, Sens
(%).
V
IOUT(Q)VCC
100
Sens
100
‰
VCC /
VCC
VCC /
/ V
IOUT(Q)5V
5 V
/ Sens
5 V
(%), is defined as:
RAT
5V
Output Voltage versus Sampled Current
Accuracy at 0 A and at Full-Scale Current
–IP (A)
IP(min)
vrOe $Temp erature
Accuracy
Accuracy
25°C Only
Increasing V
0 A
Average
V
IOUT
(V)
IOUT
Accuracy
25°C Only
Full Scale
IP(max)
Accuracy
vrOe $Temp erature
+IP (A)
Accuracy (E
). The accuracy represents the maximum devia-
TOT
tion of the actual output from its ideal value. This is also known
as the total output error. The accuracy is illustrated graphically in
the output voltage versus current chart at right.
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
ACS712
Definitions of Dynamic Response Characteristics
Power-On Time (tPO). When the supply is ramped to its operating voltage, the device requires a finite time to power its internal
components before responding to an input magnetic field.
Power-On Time, t
voltage to settle within ±10% of its steady state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
, is defined as the time it takes for the output
PO
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Rise time (tr). The time interval between a) when the device
reaches 10% of its full scale value, and b) when it reaches 90%
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the device, in which ƒ(–3 dB) = 0.35 / tr.
Both tr and t
RESPONSE
are detrimentally affected by eddy current
losses observed in the conductive IC ground plane.
Power on Time versus External Filter Capacitance
200
180
160
140
120
100
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Chopper Stabilization Technique
Chopper Stabilization is an innovative circuit technique that is
used to minimize the offset voltage of a Hall element and an associated on-chip amplifier. Allegro patented a Chopper Stabilization technique that nearly eliminates Hall IC output drift induced
by temperature or package stress effects. This offset reduction
technique is based on a signal modulation-demodulation process.
Modulation is used to separate the undesired DC offset signal
from the magnetically induced signal in the frequency domain.
Then, using a low-pass filter, the modulated DC offset is suppressed while the magnetically induced signal passes through
Regulator
Hall Element
the filter. As a result of this chopper stabilization approach, the
output voltage from the Hall IC is desensitized to the effects
of temperature and mechanical stress. This technique produces
devices that have an extremely stable Electrical Offset Voltage,
are immune to thermal stress, and have precise recoverability
after temperature cycling.
This technique is made possible through the use of a BiCMOS
process that allows the use of low-offset and low-noise amplifiers
in combination with high-density logic integration and sample
and hold circuits.
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Typical Applications
+5 V
C
BYP
0.1 μF
C
VCC
VIOUT
FILTER
GND
8
7
6
5
1
IP+
2
IP+
I
ACS712
P
3
IP–
4
IP–
R
F
10 kΩ
OUT
0.1 μF
R1
1 MΩ
C
F
1 nF
R2
33 kΩ
Application 2. Peak Detecting Circuit
+5 V
C
BYP
0.1 μF
VCC
VIOUT
FILTER
GND
8
7
R
F
2 kΩ
6
5
1
IP+
2
IP+
ACS712
I
P
3
IP–
4
IP–
V
PEAK
C2
0.1 μF
R4
10 kΩ
V
OUT
+
–
R3
330 kΩ
U1
LT11 78
D1
1N914
C1
0.1 μF
V
Q1
2N7002
RESET
I
+5 V
C
BYP
0.1 μF
1
IP+
2
VIOUT
IP+
ACS712
P
3
FILTER
IP–
4
IP–
VCC
GND
R1
100 kΩ
R2
100 kΩ
8
7
R
F
1 kΩ
6
C
F
0.01 μF
5
LM321
1
+
5
4
–
3
2
R3
3.3 kΩ
V
OUT
C1
1000 pF
Application 3. This configuration increases gain to 610 mV/A
(tested using the ACS712ELC-05A).
+5 V
C
V
OUT
C
1 nF
R1
10 kΩ
F
D1
1N4448W
C1
A-to-D
Converter
BYP
0.1 μF
1
VCC
IP+
2
VIOUT
IP+
I
ACS712
P
3
FILTER
IP–
4
IP–
GND
R1
33 kΩ
R
1
U1
LMV7235
PU
100 kΩ
Fault
R2
100 kΩ
8
V
7
OUT
6
C
F
1 nF
5
4
5
–
3
+
2
D1
1N914
Application 4. Rectified Output. 3.3 V scaling and rectification application
for A-to-D converters. Replaces current transformer solutions with simpler
ACS circuit. C1 is a function of the load resistance and filtering desired.
R1 can be omitted if the full range is desired.
Application 5. 10 A Overcurrent Fault Latch. Fault threshold set by R1 and
R2. This circuit latches an overcurrent fault and holds it until the 5 V rail is
powered down.
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
ACS712
Improving Sensing System Accuracy Using the FILTER Pin
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
In low-frequency sensing applications, it is often advantageous
to add a simple RC filter to the output of the device. Such a lowpass filter improves the signal-to-noise ratio, and therefore the
resolution, of the device output signal. However, the addition of
an RC filter to the output of a sensor IC can result in undesirable
device output attenuation — even for DC signals.
Signal attenuation, V
, is a result of the resistive divider
AT T
effect between the resistance of the external filter, RF (see
Application 6), and the input impedance and resistance of the
customer interface circuit, R
. The transfer function of this
INTFC
resistive divider is given by:
R
Even if RF and R
INTFC
∆V
INTFC
ATT
=
⎛
V
⎜
IOUT
⎜
R
+ R
F
⎝
are designed to match, the two individual
INTFC
⎞
.
⎟
⎠
resistance values will most likely drift by different amounts over
+5 V
Pin 3 Pin 4
IP– IP–
Application 6. When a low pass filter is constructed
externally to a standard Hall effect device, a resistive
divider may exist between the filter resistor, RF, and
the resistance of the customer interface circuit, R
This resistive divider will cause excessive attenuation,
as given by the transfer function for V
ATT
.
INTFC
.
0.1 MF
temperature. Therefore, signal attenuation will vary as a function
of temperature. Note that, in many cases, the input impedance,
R
, of a typical analog-to-digital converter (ADC) can be as
INTFC
low as 10 k.
The ACS712 contains an internal resistor, a FILTER pin connection to the printed circuit board, and an internal buffer amplifier.
With this circuit architecture, users can implement a simple
RC filter via the addition of a capacitor, CF (see Application 7)
from the FILTER pin to ground. The buffer amplifier inside of
the ACS712 (located after the internal resistor and FILTER pin
connection) eliminates the attenuation caused by the resistive
divider effect described in the equation for V
. Therefore, the
AT T
ACS712 device is ideal for use in high-accuracy applications
that cannot afford the signal attenuation associated with the use
of an external RC low-pass filter.
VCC
Cancellation
Dynamic Offset
Gain
Voltage
Regulator
Amp
Pin 8
Temperature
Coefficient
To all subcircuits
Filter
Trim Control
Allegro ACS706
Out
Offset
VIOUT
Pin 7
R
F
N.C.
Pin 6
Low Pass Filter
C
1 nF
F
Resistive Divider
Input
Application
Interface
Circuit
R
INTFC
Application 7. Using the FILTER pin
provided on the ACS712 eliminates the
attenuation effects of the resistor divider
between R
cation 6.
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
with
2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Package LC, 8-pin SOIC
4.90 ±0.10
8
A
21
8X
C0.10
0.51
0.31
1.27 BSC
For Reference Only; not for tooling use (reference MS-012AA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
Branding scale and appearance at supplier discretion
B
C
Reference land pattern layout (reference IPC7351
SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all
D
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances
3.90 ±0.10 6.00 ±0.20
Branded Face
SEATING
SEATING
PLANE
PLANE
1.75 MAX
0.25
0.10
8°
0°
0.25
0.17
1.04 REF
1.27
0.40
0.25 BSC
SEATING PLANE
C
C
GAUGE PLANE
8
0.65
1.75
21
PCB Layout Reference View
C
NNNNNNN
TPP-AAA
LLLLL
1
B
Standard Branding Reference View
N = Device part number
T = Device temperature range
P = Package Designator
A = Amperage
L = Lot number
Belly Brand = Country of Origin
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
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