ALLEGRO A8601 Service Manual

A8601

Multiple-Output Regulator for Automotive LCD Displays

Features and Benefits

• Automotive Grade AEC-Q100 qualified

• Five individual output supplies

• Independent control of each output voltage

• 350 kHz to 2.25 MHz switching frequency with external
synchronization capability

• <10 μA shutdown current

• Preprogrammed power-up and shutdown sequences

• Overcurrent, overvoltage, short circuit, and thermal
overload protection

Applications:

• GPS

• Infotainment

• Medium LCDs

Package: 28-pin TSSOP with exposed
thermal pad (suffix LP)

Description

The A8601 is a fixed frequency, multiple-output supply for
LCD bias. Its switching frequency can be either programmed
or synchronized with an external clock signal between 350 kHz
and 2.25 MHz, to minimize interference with AM and FM
radio bands.

A total of five output voltages are provided, from three linear
regulators and two charge-pump regulators. Each output
voltage can be adjusted independently. During power-up and
shutdown, the outputs are turned on and off in preprogrammed
sequences, to meet the sequencing requirements for specific
LCD panels.

Short circuit protection is provided for all outputs. The boost
switch is protected against overcurrent and overvoltage. Input
disconnect protection is achieved by driving an external
P-MOSFET.

28-pin exposed thermal pad TSSOP package allows operation
at high ambient temperatures. It is lead (Pb) free with 100%
matte-tin leadframe plating.

Not to scale

VIN

External Sync

1.5 to 3.2 V

System Block Diagram

Optional

R

SC

Q1

INS GATE SW

VIN

EN1

EN2

FSET_SYNC

V

VIN

FAULT
VINAMP

A8601

D1L1

OUT

DVDD

AVDD

VGH

VGL

VCOM

V

DVDD

V

AVDD

V

VGH

V

VGL

V

VCOM

3.3 V

5 to 14 V

LCD Panel

10 to 25 V

+

– 5 to –12 V

+

3 to 6 V

+

Output voltages shown are
for typical LCD Panel

A8601-DS, Rev. 1

A8601

Multiple-Output Regulator for Automotive LCD Displays

Selection Guide

Part Number Packing* Programming

A8601KLPTR-T 4000 pieces per 13-in. reel

*Contact Allegro

®

for additional packing options.

Contact Allegro Sales for

VCOM regulator factory trim option

Absolute Maximum Ratings

1,2

Characteristic Symbol Notes Rating Unit

VIN and INS Pin Voltage V

SW Pin Voltage

3,4

VIN

V

OUT Pin Voltage V

AVDD and FB2 Pin Voltage V

AVDD

CP11 Pin Voltage V

CP12 Pin Voltage V

VGH Pin Voltage V

FB4 Pin Voltage V

CP21 Pin Voltage V

V

V

CP22

EN1

V

V

CP22, VGL and FB3 Pin Voltage

EN1, EN2, and ¯F¯ ¯A

¯¯¯U ¯¯L¯ ¯T¯

Pin Voltage

BIAS Pin Voltage V

VCOM Pin Voltage V

V

PGND and GNDVCOM Pin Voltage

All other pins

5

PGND

V

GNDVCOM

Operating Ambient Temperature T

, V

SW

OUT

, V

CP11

CP12

VGH

FB4

CP21

, V

FB3

, V

FAULT

BIAS

VCOM

– –0.3 to 7 V

A

All voltages measured with respect to GND –0.3 to 6.5 V

INS

Continuous –0.6 to 22 V

Voltage spikes (pulse width < 100 ns) –1 to 40 V

–0.3 to 22 V

FB2

Positive charge pump

–0.3 to

V

OUT

–0.3 to

V

CP12

Positive charge pump –0.3 to 27 V

Positive charge pump –0.3 to 27 V

Positive charge pump

–0.3 to

V

VGH

Negative charge pump –0.3 to 14 V

,

VGL

Negative charge pump –14 to 0.3 V

,

EN2

–0.3 to 5.5 V

–0.3 to lower of:

5.5 or V

–0.3 to lower of:
7 or V

AVDD

,

–0.3 to 0.3 V

K temperature range –40 to 125 ºC

+ 0.3

+ 0.3

+ 0.3

VIN

+ 0.3

+ 0.3

V

V

V

V

V

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature T

1

Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings

stg

–55 to 150 ºC

only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is
not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability.

2

All voltages referenced to AGND.

3

The SW pin has internal clamp diodes to GND. Applications that forward bias this diode should take care not to exceed the IC package

power dissipation limits. Note: Exact energy specification to be determined.

4

The switch DMOS is self-protected. If voltage spikes exceeding 40 V are applied, the device would conduct and absorb the energy safely.

5

When V

= 0 (no power), all inputs are limited by -0.3 to 5.5 V.

VIN

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance

*Additional thermal information available on the Allegro website.

R

θJA

On 4-layer PCB based on JEDEC standard 28 ºC/W

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

2

A8601

Multiple-Output Regulator for Automotive LCD Displays

Table of Contents

Characteristic Performance 10
Functional Description 15

Linear Regulators 15
VCOM Regulator 15
Charge Pumps 16
Boost Controller 18
Switching Frequency 19
Continuous Conduction Mode Operation 20
Input Disconnect Switch 21
FAULT Conditions 22
Pre-Output Fault Detection 23
General Fault Detection 23

Application Information 24

Output Voltage Selection 24
Output Capacitance 25

Operating with Separate VIN and
Boost Supplies 26
Thermal Analysis 26
Component Selection Recommendations 28
I/O pin Equivalent Circuit Diagrams 29

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

3

A8601

Multiple-Output Regulator for Automotive LCD Displays

Functional Block Diagram

5 V DC to DC

Converter

(

4V )

min.

6

V

DVDD

3.3V

External

.

Sync

FSET_SYNC

C

COMP

V

VIN

FAULT

VIN

DVDD

FB1

EN1

COMP

EN2

R

INS

SC

OCP

LDO

1

Enable/

Disable

Fault

Q1

Drive

GATE

REG

Boost

Regulator

with
Soft
Start

SW

OFF

OFF

ON

OFF

D1L1

ON

OFF

ON

ON

OUT

X1.9 4

OP AMP

ON

+

LDO

2

+

5

2x

Charge

Pump

4

–

–

90%

C

OUT

6

+

C

Microprocessor

+

C

+

V

AVDD

10V

AVDD

1.5 to 3.2 V
from

6

V

VCOM

3 to6 V

VCOM

6

V

VGH

18 V

AVDD

FB2

VINAMP

VCOM

GNDVCOM

C

FLY1

CP11

CP12
VGH

FB4

BIAS

AGND

V

IN

BIAS

Regulat or

3.6 V

See Terminal List Table

1 to 5

6

Output voltages shown are for a typic

ON

OFF

OFF

C

FLY2

+

10%

-

Inverted

Charge

Pump

3

+

–

al LCD panel

90 %

CP21
CP22

VGL

FB

3

+

PGND

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

V

-8 V

6

VGL

4

A8601

Multiple-Output Regulator for Automotive LCD Displays

Pin-out Diagram

GATE

INS

VIN

DVDD

FB1

COMP

VINAMP

VCOM

GNDVCOM

FSET_SYNC

BIAS

FAULT

EN1

EN2

Terminal List Table

Number Name Function

1 GATE Gate driver for input disconnect P-MOSFET

2 INS

3 VIN Input supply voltage (4.0 to 5.5 V) for the IC

4 DVDD

5

FB1

(DVDD)

6 COMP

7 VINAMP Control voltage from external microprocessor

8 VCOM

9 GNDVCOM Ground reference for VCOM

10 FSET_SYNC

11 BIAS

12 ¯F¯ ¯A

¯¯¯U ¯¯L¯ ¯T¯

13 EN1

14 EN2

High-side sense for input overcurrent
detection

Output from internal LDO (item 1 in Functional
Block Diagram) powered by VIN

Connect to resistor divider network to set
DVDD

Compensation pin, connect to external COMP
capacitor

Output from operational amplifier (item 5 in
Functional Block Diagram), controlled by
VINAMP

Input for synchronizing boost and charge
pump signals switching frequency to external
clock signal; alternatively, it can be connected
to an external resistor to set the switching
frequency

Output from internal 3.6 V bias regulator;
connect to GND via 0.1 μF ceramic capacitor

Open-drain output, pulls low in error condition

Enable pin for DVDD output; system can only
be enabled after V
(refer to Startup Timing Diagram)

is above UVLO level

VIN

Enable pin for the voltage outputs other than
DVDD; it can be activated only after V
above UVLO and EN1 = high.

VIN

28

1

2

3

4

5

6

PAD

7

8

9

10

11

12

13

14

SW

27

PGND

26

OUT

25

AVD D

24

FB2

23

CP11

22

CP12

21

VGH

20

FB4

19

CP21

18

CP22

17

VGL

16

FB3

15

AGND

Number Name Function

15 AGND

16

FB3

(VGL)

17 VGL

Analog GND reference for signals; connect to
ground plane

Connect to resistor divider network to set V

VGL

Inverted charge pump output
(item 3 in Functional Block Diagram)

Capacitor terminal for inverted charge pump

18 CP22

(item 3 in Functional Block Diagram); refer to
Negative Charge Pump section for usage

19 CP21

20

FB4

(VGH)

21 VGH

22 CP12

23 CP11

24

FB2

(AVDD)

25 AVDD

26 OUT

Capacitor terminal for inverted charge pump
(item 3 in Functional Block Diagram)

Connect to resistor divider network to set V

VGH

2x charge pump (item 4 in Functional Block
Diagram) output

Capacitor terminals for charge pump
(item 4 in Functional Block Diagram)

Connect to external resistor network to set
V

AVDD

Output from internal LDO (item 2 in Functional
Block Diagram) powered by V

OUT

Connect to boost output for internal LDO and
charge pump regulators

Power ground for internal boost switch;

27 PGND

connect this pin to ground terminal of
output ceramic capacitor(s)

28 SW Boost converter switch node

is

– PAD

Exposed pad (substrate of IC); solder to GND
plane for better thermal conduction

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

5

A8601

Multiple-Output Regulator for Automotive LCD Displays

ELECTRICAL CHARACTERISTICS

V

= –8 V, TJ = TA = 25°C, except indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless otherwise specified

VGL

1

Valid at V

= 5 V, EN1 = EN2 = high, fSW = 2 MHz, V

VIN

DVDD

= 3.3 V, V

AVDD

= 10 V, V

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Input Voltage and Current

Input Voltage V

VIN Pin Undervoltage Lockout
(UVLO) Threshold

VIN Pin UVLO Hysteresis V

Shutdown Bias Current I

Standby Bias Current I

Operating Bias Current I

V

UVLO(HYS)

VINBIAS(SD)

VINBIAS(STB)

VINBIAS(OP)

VIN

UVLO

V

rising 3.6 – 4.0 V

VIN

Current into VIN pin, EN1 = low –550μA

EN1 = high, EN2 = low, no load at DVDD pin – 2 – mA

EN1 = high, EN2 = high – 6.5 – mA

4.0 – 5.5 V

– 0.15 0.25 V

Boost Switch

Switch Peak Current Limit I

Switch On-Resistance R

Switch Minimum On-Time t

Switch Minimum Off-Time t

SW Pin Leakage Current I

OUT Pin Leakage Current I

SW Pin Secondary Overvoltage
Protection (OVP)

SW Pin Secondary OVP Minimum
Pulse Width

4

V

t

SW(MAX)

DS(on)ISW

ON(MIN)

OFF(MIN)

SW(LKG)VSW

OUT(LKG)VOUT

SW(OVP)

SW(OVP)VSW

Cycle-by-cycle current limit 1.3 – 2.0 A

= 0.5 A – 0.5 – Ω

50 72 95 ns

33 50 75 ns

= 5 V, EN1 = low – 0.1 – μA

= 5 V, EN1 = low – 0.1 – μA

17.4 19.2 21.2 V

≥ OVP level – 40 – ns

Switching Frequency / Synchronization

FSET_SYNC Pin Voltage V

FSET_SYNC Pin Current I

FSETSYNC

FSETSYNC

Switching Frequency f

Synchronization Frequency f

Synchronization Minimum On-Time t

Synchronization Minimum Off-Time t

SYNC(ON)

SYNC(OFF)

SW

SYNC

Without using external synchronization signal

R

FSET_SYNC

= 5.1 kΩ 1.81 2.0 2.17 MHz

External logic signal connected to
FSET_SYNC pin

– 1.0 – V

34 – 220 μA

0.35 – 2.25 MHz

150 – – ns

150 – – ns

Input Disconnect

= V

GATE Pin Sink Current I

GATE Pin Source Current I

GATE Voltage at Off Condition V

INS Trip Point V

INS Trip Blanking Time t

GATE(SNK)VGATE

GATE(SRC)VGATE

GATE(OFF)

INS(TRIP)

INS(BLANK)

EN1 = EN2 = low, or fault tripped – V

Between VIN and INS pins 85 100 115 mV

Sensed voltage = 2 × input current limit 1.5 – 3 μs

, no fault – 100 – μA

VIN

= 0 V, fault tripped – 130 – mA

VIN

= 20 V,

VGH

–V

Continued on the next page…

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

6

A8601

Multiple-Output Regulator for Automotive LCD Displays

ELECTRICAL CHARACTERISTICS

V

= 20 V, V

VGH

otherwise specified

Feedback Pins

Feedback Sense Voltage V

Output Overvoltage Fault Threshold V

Output Undervoltage Fault Threshold V

Feedback Input Currents I

Feedback Load Resistance

Output Regulators

DVDD Output Voltage V

AVDD Output Voltage V

VCOM Output Voltage V

VGH Output Voltage V

VGL Output Voltage V

Dropout for DVDD Regulator V

Boost Minimum Headroom for AVDD
Regulator

Boost Minimum Headroom for VGH
Regulator

Boost Minimum Headroom for VGL
Regulator

Output Pull-Down Resistor During
Shutdown (AVDD, VCOM, VGH, VGL)

Logic Inputs

Input Logic High V

Input Logic Low V

Internal Pull-Down Resistance to AGND R

= –8 V, TJ = TA = 25°C, except indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless

VGL

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

2

V

V

V

R

1

(continued) Valid at V

FB1, FB2, and FB4 pins – 2.40 – V

FBx

FB3 pin – –1.8 – V

FB1, FB2, and FB4 pins; V

FBx(OV)

V

falling – –2.16 – V

FB3

FB1, FB2, and FB4 pins; V

FBx(UV)

V

rising – –1.44 – V

FB3

FB1, FB2, and FB4 pins; V

FBx

V

= –1.8 V – 0.5 – μA

FB3

FB1 pin 9 10 11 kΩ

R

FB2 pin 24 25 26 kΩ

FBx

FB3 and FB4 pins 49 50 51 kΩ

DVDDVVIN

AVDD

VCOMVVIN

VGH

VGL

DVDD(DO)

AVDD(DO)

VGH(DO)

VGL(DO)

OUTPD

IH

IL

ENx(PD)

= 4.0 to 5.5 V 2.4 – V

V

= 4.0 to 5.5 V 4.4 – 14.8 V

VIN

= 4.0 to 5.5 V, V

V

= 4.0 to 5.5 V 2.4 – 26 V

VIN

V

= 4.0 to 5.5 V –12.9 – –5 V

VIN

Between VIN and DVDD pins;
V

= 2.33 V, I

FB1

Defined as V
I

= 100 mA

OUT

Defined as V
V

= 2.33 V, I

FB4

Defined as V

= –1.75 V, I

V

FB3

EN1 = high, EN2 = low – 250 – Ω

EN1, EN2, FSET_SYNC pins 1.8 – – V

EN1, EN2, FSET_SYNC pins – – 0.8 V

EN1, EN2 pins – 100 – kΩ

OUT

OUT

OUT

= 5 V, EN1 = EN2 = high, fSW = 2 MHz, V

VIN

rising – 2.88 – V

FBx

falling – 1.92 – V

FBx

= 2.4 V – –0.5 – μA

FBx

OUT

– V

– V

OUT

– (–V

OUT

> V

AVDD

= 50 mA

; V

AVDD

/ 2;

VGH

= 8 mA

VGL

= –8 mA

);

+ 1.5 V 2.9 – 6.8 V

VCOM

= 2.33 V,

FB2

DVDD

= 3.3 V, V

VIN

= 10 V,

AVDD

– 0.6 V

– – 0.6 V

–2–V

– 2.4 – V

– 3.6 – V

Continued on the next page…

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

7

A8601

Multiple-Output Regulator for Automotive LCD Displays

ELECTRICAL CHARACTERISTICS

V

= 20 V, V

VGH

otherwise specified

Output Current Capacity

DVDD Overcurrent Protection (OCP)
Trip Level

AVDD OCP Trip Level I

VCOM OCP Trip Level i

VGH OCP Trip Level i

VGL OCP Trip Level i

Output Voltage Accuracy

DVDD Load Regulation V

AVDD, VGL and VGH Load
Regulation

DVDD Accuracy

AVDD Accuracy

VGH Accuracy

VGL Accuracy

VCOM Operational Amplifier

VCOM Gain

VCOM Load Regulation

VCOM Temperature Coefficient

Input Resistance to AGND R

Dropout for VCOM from AVDD V

¯F¯ ¯

¯¯¯U ¯¯L¯ ¯T¯

A

Pin

¯F¯ ¯

¯¯¯U ¯¯L¯ ¯T¯

A

Pull-Down Voltage V

¯F¯ ¯

¯¯¯U ¯¯L¯ ¯T¯

A

Pin Leakage Current V

= –8 V, TJ = TA = 25°C, except indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless

VGL

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

I

DVDD(OCP)

AVDD(OCP)

3

3

3

3

4

4

4

err

err

V

TC

VINAMP(PD)

VCOM(DO)VAVDD

FAULT(PD)

FAULT(LKG)

1

(continued) Valid at V

Includes i

VCOM

VGH

VGL

DVDDregVDVDD

V

err

err

Current into VGL pin 14 – 32 mA

xregILOAD

DVDDVDVDD

AVDDVAVDD

VGHVVGH

V

VGL

VCOM

= 3.3 V, I

= 10% to 100% of I

= 3.30 V –2.5 – 2.5 %

= 10.0 V –2.1 – 2.1 %

= 20.0 V –2.5 – 2.5 %

= –8.0 V –2.5 – 2.5 %

VGL

Defined as V

A

VCOM

VCOMregILOAD

1.5 V < V
85°C, I

–30°C < TA < 85°C, I

VCOM

VINAMP

LOAD

= 5 to 50 mA –5 – 5 mV

VINAMP pin – 100 – kΩ

= 7 V, I

Fault condition asserted,
pull-up current = 1 mA

Fault condition cleared, pull-up to 5 V – – 1 μA

= 5 V, EN1 = EN2 = high, fSW = 2 MHz, V

VIN

DVDD

= 3.3 V, V

50 – 90 mA

200 – 350 mA

60 – 110 mA

14 – 32 mA

= 10 to 50 mA –0.1 – 0.1 V

LOAD

(min) –0.1 – 0.1 V

x(OCP)

/ V

VCOM

< 3.21 V, –30°C < TA <

VINAMP

;

1.92 1.94 1.96 V / V

= 25 mA

= 25 mA –50 – 50 μV/°C

LOAD

= 60 mA – – 1.5 V

VCOM

– – 0.4 V

AVDD

= 10 V,

Continued on the next page…

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

8

A8601

Multiple-Output Regulator for Automotive LCD Displays

ELECTRICAL CHARACTERISTICS

V

VGH

= 20 V, V

= –8 V, TJ = TA = 25°C, except indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless

VGL

1

(continued) Valid at V

= 5 V, EN1 = EN2 = high, fSW = 2 MHz, V

VIN

DVDD

= 3.3 V, V

AVDD

otherwise specified

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Fault Timers

Soft Start Time-Out t

SS(TO)

Maximum time allowed for any output to
reach 90% of its target

Maximum time allowed for VGH to fall to

Shutdown Time-Out t

Overcurrent Protection (OCP)
Time-Out

Restart Delay t

t

RESTART

Fault Counter Reset Time t

SDN(TO)

OCP(TO)

fault

10% and VGL to 30% of their respective
targets; EN1 = high, EN2 = low

Maximum time allowed for any output to
stay in an overcurrent fault condition before
shutdown

Delay time after fault shutdown until the next
retry (repeats until Fault counter = 8)

Time required after setting EN1 = low until
Fault counter clears

Thermal Shutdown (TSD) Protection

TSD Threshold T

TSD Hysteresis

1

For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as

going into the node or pin (sinking).

2

Net parallel resistance required at FBx pin in order to meet accuracy.

3

Output voltage is set to required nominal value using external sense resistor network. Output current at 50% of minimum OCP trip level. Accuracy

does not include mismatch error caused by external sense resistor network.

4

Ensured by design and characterization, not production tested.

4

T

TSD(HYS)

Temperature rising – 165 – °C

TSD

40 50 60 ms

40 50 60 ms

40 50 60 ms

80 100 120 ms

1––μs

–20–°C

= 10 V,

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

9

A8601

Multiple-Output Regulator for Automotive LCD Displays

Characteristic Performance

Startup and Shutdown Sequences (Normal Operation)

VIN

EN1

EN2

DVDD

AVDD

VGL

VGH

90%

t<100 ms

90%

30%

90%

90%

10%

VINAMP

VCOM

Notes:

• Normal system startup should follow the above sequence (VIN → EN1 → EN2).

• EN1 can only be asserted after VIN is above UVLO level, V
ignored until VIN rises above V

• EN2 can only be asserted when DVDD is >90% target voltage. If asserted before that, it is ignored
until the condition is met.

• VGH is enabled only after the magnitude of VGL has reached >90% of its target voltage.

• VCOM output is enabled only after VGH has reached >90% of its target voltage. (A valid VINAMP
must be asserted prior to this.)

• System shutdown should start with EN2 = low, followed by EN1 = low.

• VGL shutdown can only start after VGH has dropped to 10% its original target voltage, or the VGH
shutdown time-out interval has expired.

• EN1 = low can only be asserted when VGL has fallen below 30% of its target voltage. If asserted
before that, it is ignored until the condition is met or the VGL shutdown time-out interval has
expired.

UVLO

.

. If asserted before that, it is

UVLO

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

10