Allegro A6B273KLW, A6B273KA Datasheet
6B273
Data Sheet
26180.122
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
LOGIC
V
DD
LATCHES
20
SUPPLY
19
IN
8
IN
18
7
OUT
17
8
16
OUT
7
OUT
15
6
14
OUT
5
13
IN
6
12
IN
5
11
STROBE
Dwg. PP-015-2
OUT
OUT
OUT
OUT
1
2
IN
1
3
IN
2
4
1
5
2
6
3
7
4
8
IN
3
9
IN
4
10
LATCHES
CLEAR
GROUND
Note that the A6B273KA (DIP) and the A6B273KLW
(SOIC) are electrically identical and share a common
terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T
= 25°C
A
Output Voltage, VO............................... 50 V
Output Drain Current,
Continuous, IO.......................... 150 mA*
Peak, IOM................................... 500 mA†
Single-Pulse Avalanche Energy,
EAS................................................. 30 mJ
Logic Supply Voltage, VDD.................. 7.0 V
Input Voltage Range,
VI................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD........................................... See Graph
Operating Temperature Range,
TA................................. -40°C to +125°C
Storage Temperature Range,
TS................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
8-BIT LATCHED
DMOS POWER DRIVER
The A6B273KA and A6B273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power
loads. The CMOS inputs and latches allow direct interfacing with
microprocessor-based systems. Use with TTL may require appropriate
pull-up resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs
are capable of sinking up to 500 mA. Similar devices with reduced
r
are available as the A6273KA/KLW.
DS(on)
The A6B273KA is furnished in a 20-pin dual in-line plastic
package. The A6B273KLW is furnished in a 20-lead wide-body,
small-outline plastic package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current
requirements, and low on-state resistance allow both devices to sink
150 mA from all outputs continuously, to ambient temperatures over
85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 150 mA Output Current (all outputs simultaneously)
■ 5 Ω Typical
■ Low Power Consumption
■ Replacements for TPIC6B273N and TPIC6B273DW
Always order by complete part number:
Part Number Package R
A6B273KA 20-pin DIP 55°C/W 25°C/W
A6B273KLW 20-lead SOIC 70°C/W 17°C/W
r
DS(on)
θJA
R
θJC
6B273
8-BIT LATCHED
DMOS POWER DRIVER
2.5
2.0
SUFFIX 'A', R = 55
1.5
1.0
0.5
0
25
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
SUFFIX 'LW
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
IN
θ
J
A
', R = 70
θ
J
A
°C/W
°C/W
V
Dwg. GS-004A
DD
LOGIC SYMBOL
1
11
2
3
18
R
C1
1D 4
1D
1D8
1D9
1D12
1D13
1D
1D19
5
6
7
14
15
16
17
Dwg. FP-046-1
OUT
Dwg. EP-010-16
DMOS POWER DRIVER OUTPUTLOGIC INPUTS
FUNCTION TABLE
Inputs
CLEAR STROBE IN
X
LXXH
HHL
HLH
HLXR
L = Low Logic Level
H = High Logic Level
X = Irrelevant
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
W
Copyright © 2000, Allegro MicroSystems, Inc.
OUT
X
Dwg. EP-063
FUNCTIONAL BLOCK DIAGRAM
6B273
8-BIT LATCHED
DMOS POWER DRIVER
IN
STROBE
IN
LOGIC
SUPPLY
IN
IN
IN
1
2
V
DD
3
4
5
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
www.allegromicro.com
IN
IN
IN
CLEAR
(ACTIVE LOW)
6
7
8
D
C1
CLR
D
C1
CLR
D
C1
CLR
OUT
6
OUT
7
OUT
8
GROUND
Dwg. FP-016-2
6B273
8-BIT LATCHED
DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD............... 4.5 V to 5.5 V
High-Level Input Voltage, V
Low-level input voltage, V
............................ ≥ 0.85V
IH
................................. ≤0.15V
IL
DD
DD
ELECTRICAL CHARACTERISTICS at T
= +25°C, V
A
= 5 V, tir = t
DD
≤ 10 ns (unless otherwise
if
specified).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Logic Supply Voltage V
Output Breakdown V
(BR)DSXIO
Voltage
Off-State Output I
Current
Static Drain-Source r
On-State Resistance
Nominal Output I
Current
Logic Input Current I
Prop. Delay Time t
DD
DSX
DS(on)
ON
IH
I
IL
PLH
Operating 4.5 5.0 5.5 V
= 1 mA 50 — — V
VO = 40 V, V
VO = 40 V, VDD = 5.5 V, T
IO = 100 mA, V
IO = 100 mA, VDD = 4.5 V, T
IO = 350 mA, V
V
= 0.5 V, T
DS(on)
VI = V
= 5.5 V — — 1.0 µA
DD
VI = 0, V
= 5.5 V — 0.1 5.0 µA
DD
= 125°C — 0.15 8.0 µA
A
= 4.5 V — 4.2 5.7 Ω
DD
= 125°C— 6.8 9.5 Ω
A
= 4.5 V (see note) — 5.5 8.0 Ω
DD
= 85°C—90—mA
A
= 5.5 V — — -1.0 µA
DD
IO = 100 mA, CL = 30 pF — 150 — ns
t
Output Rise Time t
Output Fall Time t
Supply Current I
DD(OFF)
I
DD(ON)
PHL
r
f
IO = 100 mA, CL = 30 pF — 90 — ns
IO = 100 mA, CL = 30 pF — 200 — ns
IO = 100 mA, CL = 30 pF — 200 — ns
V
= 5.5 V, Outputs off — 20 100 µA
DD
V
= 5.5 V, Outputs on — 150 300 µA
DD
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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