Allegro A6A259KLB, A6A259KA Datasheet
6A259
Data Sheet
26186.121
ADVANCE INFORMATION
(Subject to change without notice)
March 22, 2000
A6A259KA (DIP)
OUT
2
1
OUT
3
2
S
1
3
LOGIC
(MSB)
OUT
OUT
4
5
6
7
8
9
4
5
10
GROUND
POWER
GROUND
POWER
GROUND
2
S
ENABLE EN
DECODER
V
LATCHES
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO............................ 50 V
Output Drain Current,
Continuous, IO...................... 350 mA*
Peak, IOM........................... 1100 mA*†
Peak, IOM.................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS............................................. 75 mJ
Logic Supply Voltage, VDD.............. 7.0 V
Input Voltage Range,
VI............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD....................................... See Graph
Operating Temperature Range,
TA............................. -40°C to +125°C
Storage Temperature Range,
TS............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical
charges.
OUT
1
20
19
OUT
0
S0 (LSB)
18
LOGIC
17
DD
SUPPLY
POWER
16
GROUND
POWER
15
GROUND
14
CLEAR
DATA
13
OUT
7
12
6
OUT
11
Dwg. PP-050-4
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6A259KA and A6A259KLB combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pullup resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6A259KA/KLB
DMOS open-drain outputs are capable of sinking up to 500 mA.
The A6A259KA is furnished in a 20-pin dual in-line plastic package. The A6A259KLB is furnished in a 24-lead wide-body, smalloutline plastic batwing package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150
mA from all outputs continuously, to ambient temperatures over 85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 350 mA Output Current (all outputs simultaneously)
■ 1 Ω Typical
■ Internal Short-Circuit Protection
■ Low Power Consumption
■ Replacements for TPIC6A259N and TPIC6A259DW
Always order by complete part number:
Part Number Package R
A6A259KA 20-pin DIP 55°C/W 25°C/W —
A6A259KLB 24-lead SOIC 55°C/W — 6°C/W
r
DS(on)
θJA
R
θJC
R
θJT
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
5
SUFFIX 'LB', R = 6.0°C/W
θJT
4
3
SUFFIX 'A', R = 25°C/W
θJC
2
1
R = 55°C/W
θJA
0
25
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
50 75 100 125 150
TEMPERATURE IN °C
IN
Dwg. GP-049-5
V
DD
A6A259KLB (SOIC)
1
OUT
2
2
OUT
3
3
S
1
LOGIC
GROUND
GROUND
GROUND
GROUND
GROUND
S
ENABLE EN
4
POWER
5
POWER
6
POWER
7
POWER
817
2
(MSB)
9
10
11
OUT
4
12
OUT
5
DECODER
LATCHES
24
OUT
1
23
0
OUT
22
S0 (LSB)
LOGIC
21
V
DD
SUPPLY
POWER
20
GROUND
POWER
19
GROUND
POWER
18
GROUND
POWER
GROUND
16
CLEAR
15
DATA
14
OUT
7
13
OUT
6
Dwg. PP-050-3A
OUT
Dwg. EP-010-15
DMOS POWER DRIVER OUTPUTLOGIC INPUTS
FUNCTION TABLE
Inputs
CLEAR ENABLE DATA OUTPUT OUTPUTs Function
HLH L R
HLL H R
H H X R R Memory
LLH L H
LLL H H
L H X H H Clear
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
Addressed Other
Addressable
Latch
8-Line
Demultiplexer
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
Dwg. EP-063-5
LATCH SELECTION TABLE
Select Inputs
S2 (MSB)S1S0 (LSB) OUTPUT
LLL 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7
Addressed
FUNCTIONAL BLOCK DIAGRAM
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
(LSB)
(MSB)
S
0
S
1
S
2
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
OUT
OUT
OUT
OUT
OUT
0
1
2
3
4
LOGIC
SUPPLY
LOGIC
GROUND
DATA
ENABLE
(ACTIVE LOW)
CLEAR
(ACTIVE LOW)
www.allegromicro.com
CLR
D
V
DD
C1
CLR
D
C1
CLR
D
C1
CLR
CURRENT LIMIT AND CHARGE PUMP
OUT
5
OUT
6
OUT
7
POWER
GROUND
Dwg. FP-047-2
Power grounds must be connected externally to a single point.
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