ALLEGRO A6821 User Manual

A6821

DABiC-5 8-Bit Serial Input Latched Sink Drivers

A merged combination of bipolar and MOS technology gives these
devices an interface fl exibility beyond the reach of standard logic

Package A
16-pin DIP

buffers and power driver arrays. Typical applications include driving
multiplexed LED displays or incandescent lamps.

The A6821 has an eight-bit CMOS shift register and CMOS control
circuitry, eight CMOS data latches, and eight bipolar current-sinking
Darlington output drivers.

The CMOS inputs are compatible with standard CMOS logic levels.
TTL circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for interface
applications requiring additional drive lines.

26185.112B

Data Sheet

Package LW

16-pin Wide Body SOIC

AB SO LUTE MAX I MUM RAT INGS

Output Voltage, V
Logic Supply Voltage, V
Input Voltage Range, V
Continuous Output Current (each output), I
Package Power Dissipation, P

A6821SA/A6821EA..................................2.1 W

A6821SLW............................................... 1.5 W

Operating Temperature Range
Ambient Temperature, T

Storage Temperature, TS..........–55°C to +150°C

Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.

.........................................50 V

OUT

...................................7 V

DD

..............–0.3 V to VDD +0.3 V

IN

OUT

D

............–20°C to +85°C

A

...500 mA

The A6821SA is furnished in a standard 16-pin plastic DIP. The
A6821EA is a 16-pin plastic DIP, capable of operation from -40°C to
+85°C. The A6821SLW is a 16-lead wide-body SOIC, for surface­mount applications. These devices are lead (Pb) free, with 100% matte
tin plated leadframes.

FEATURES

 3.3 V to 5 V logic supply range
 Power on reset (POR)
 To 10 MHz data input rate
 CMOS, TTL compatible
 –40°C operation available

 Schmitt trigger inputs for improved

noise immunity

 Low-power CMOS logic and latches
 High-voltage current-sink outputs

 Internal pull-up/pull down resistors

APPLICATIONS

 Multiplexed LED displays
 Incandescent lamps

Use the following complete part numbers when ordering:

Part Number Package Ambient

A6821SA-T 16-pin DIP –20ºC to +85ºC
A6821EA-T 16-pin DIP –40ºC to +85ºC

A6821SLW-T 16-pin wide body SOIC –20ºC to +85ºC

A6821

OUT

7.2 k 3 k

SUB

DABiC-5 8-Bit Serial Input Latched Sink Drivers

Functional Block Diagram

26185.112B

Data Sheet

CLOCK

SERIAL

DATA IN

LOGIC

GROUND

Typical Input Circuits

STROBE
OUTPUT

ENABLE

OUT1OUT

V

S E R IAL-P AR ALLE L SHIF T R E G IS T E R

LATCHE S

OUT4OUT

OUT

2

3

DD

OUT6OUT7OUT

5

LOGIC

MOS

SUB

SUPPLY

SERIAL
DATA O UT

STROBE

OUTPUT E NABLE
(ACT IVE L O W )

POWER
GROUND

V

DD

BIPOLAR

8

Typical Output Driver

ΩΩ

CLOCK

SERIAL

DATA IN

V

DD

www.allegromicro.com

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

2

A6821

Serial Shift Register Contents Serial Latch Contents Output Output Contents
Data Clock Data Strobe Enable
Input Input I

1I2I3

... I

8

Output Input I1I2I3... I

8

Input I1I2I3... I

8

R

7

R

7

R

1R2R3

... R

8

R

8

XXX...X XXL

R

1R2

... R

7

L

L

R

1R2R3

... R

8

P1P2P3... P

8

P

8

P1P2P3... P

81

P2P3... P

8

XXX...X

L

P

HH

H

H

H

R

1R2

... R

7

H

H

H...

DABiC-5 8-Bit Serial Input Latched Sink Drivers

26185.112B

Data Sheet

ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: T

Characteristic Symbol Test Conditions

Output Leakage Current I

Collector–Emitter Saturation
Voltage

Input Voltage

V

CE(SAT)

V

V

Input Resistance R

V

Serial Data Output Voltage

Maximum Clock Frequency

Logic Supply Current

Output Enable-to-Output Delay

Strobe-to-Output Delay

2

OUT(1)IOUT

V

OUT(0)IOUT

I

DD(1)

I

DD(0)

t

dis(BQ)VCC

t

en(BQ)

t

p(STH-QL)VCC

t

p(STH-QH)VCC

Output Fall Time t

Output Rise Time t

Clock-to-Serial Data Out Delay t

1

Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin.

2

Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed.

p(CH-SQX)IOUT

V

CEX

IN(1)

IN(0)

IN

= 50 V – – 10 – – 10 μA

OUT

I

= 100 mA – – 1.1 – – 1.1 V

OUT

I

= 200 mA – – 1.3 – – 1.3 V

OUT

= 350 mA – – 1.6 – – 1.6 V

I

OUT

= –200 μA 2.8 3.05 – 4.5 4.75 – V

= 200 μA – 0.15 0.3 – 0.15 0.3 V

f

c

One output on, OE = L, ST = H – – 2.0 – – 2.0 mA

All outputs off, OE = H, ST = H,
P1 through P8 = L

= 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs

VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs

= 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs

= 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs

VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs

f

VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs

r

= ±200 μA – 50 – – 50 – ns

= 25°C, logic supply operating voltage V

A

V

= 3.3 V Vdd = 5 V

dd

Min. Typ. Max. Min. Typ. Max.

2.2 – – 3.3 – – V

– – 1.1 – – 1.7 V

50 – – 50 – – kΩ

10 – – 10 – – MHz

– – 100 – – 100 μA

= 3.0 V to 5.5 V

dd

Units

Truth Table

L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State

R = Previous State
OE = Output Enable
ST = Strobe

www.allegromicro.com

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

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