Allegro A6812SLW, A6812SEP, A6812SA, A6812ELW, A6812EEP Datasheet
...
A6812xA
LOAD
1
V
SUPPLY
SERIAL
DATA OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BLANKING
GROUND
BB
2
326
20
4
19
5
18
6
17
7
16
BLNK
LATCHES
REGISTER
8
15
9
14
10
13
11
12
12
11
13
14 27
LATCHES
REGISTER
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD................... 7.0 V
Driver Supply Voltage, V
Continuous Output Current Range,
I
......................... -40 mA to +15 mA
OUT
Input Voltage Range,
V
....................... -0.3 V to VDD + 0.3 V
IN
Package Power Dissipation,
P
........................................ See Graph
D
Operating Temperature Range, T
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20
Storage Temperature Range,
T
............................... -55°C to +125°C
S
Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
................... 60 V
BB
LOGIC
28
V
DD
SUPPLY
SERIAL
27
DATA IN
OUT
OUT
25
OUT
24
OUT
23
22
OUT
21
OUT
20
OUT
19
OUT
18
OUT
17
OUT
28
16
STROBE
ST
15
CLOCK
CLK
Dwg. PP-029-7
A
°C to +85°C
26182.126A
Data Sheet
6812
DABiC-IV, 20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6812– devices combine a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6812– features an increased data input rate (com-
1
2
3
4
5
6
7
8
9
10
pared with the older UCN/UCQ5812-F) and a controlled output slew
rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they
will operate to at least 10 MHz.
A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32
bits).
The A6812– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA.
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A), surface-mount
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix
-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA from all
outputs continuously to more than +43°C (suffix -LW), +61°C (suffix
-EP), or +77°C (suffix -A).
FEATURES
■ Controlled Output Slew Rate
■ High-Speed Data Storage
■ 60 V Minimum
Output Breakdown
■ High Data Input Rate
■ PNP Active Pull-Downs
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6812SLW .
■ Low Output-Saturation Voltages
■ Low-Power CMOS Logic
and Latches
■ Improved Replacements
for TL5812–, UCN5812–,
and UCQ5812–
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812xEP A6812xLW
OUT
OUT
LOAD
1
V
BB
2
326
4
19
5
18
6
17
7
16
8
9
10
13
11
12
13
BLNK
14 27
LATCHES
REGISTER
SERIAL
DATA IN
27
LATCHES
17
10
OUT
1
OUT
26
18
9
OUT
25
OUT
24
23
22
21
20
19
OUT
Dwg. PP-059-1
SUPPLY
SERIAL
DATA OUT
OUT
20
2
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BLANKING
GROUND
15
14
12
11
20
19
OUT
4
5
18
6
7
8
9
10
11
12
12
11
OUT
SERIAL
DATA OUT
OUT
3
2
LATCHES
REGISTER
14
13
GROUND
BLANKING
LOAD
SUPPLY
1
BB
V
CLK
15
CLOCK
LOGIC
SUPPLY
28
DD
V
REGISTER
ST
16
STROBE
LATCHES
REGISTER
V
ST
CLK
TYPICAL INPUT CIRCUIT
V
DD
DD
LOGIC
28
SUPPLY
SERIAL
27
DATA IN
OUT
OUT
25
OUT
24
OUT
23
22
OUT
21
OUT
20
OUT
19
OUT
18
OUT
17
OUT
28
16
STROBE
15
CLOCK
Dwg. PP-029-8
1
2
3
4
5
6
7
8
9
10
IN
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
V
BB
OUT
Dwg. EP-021-19
2.5
SUFFIX 'EP', R = 55
SUFFIX 'A', R = 45
2.0
θJA
1.5
S
U
F
F
IX
'LW
1.0
0.5
N
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
25
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
°C/W
', R
= 66
θJA
θ
J
A
°C/W
°C
/W
Dwg. GP-024-2
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
6812
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
GROUND
OUT1OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
OUT
2
3
OUT
N
V
DD
MOS
BIPOLAR
V
BB
LOGIC
SUPPLY
SERIAL
DATA OUT
LOAD
SUPPLY
Dwg. FP-013-1
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I
1I2I3
HHR
LLR
XR
1R2R3
XXX...X X X L R1R2R3... R
P1P2P3... P
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
1R2
1R2
... I
... R
... R
... R
N-1IN
N-2RN-1
N-2RN-1
N-1RN
N-1PN
Output Input I1I2I3... I
R
N-1
R
N-1
R
N
P
N
HP1P2P3... P
X X X ... X X H L L L ... L L
N-1IN
N-1 RN
N-1 PN
Blanklng I1I2I3... I
LP1P2P3... P
N-1
N-1 PN
I
N
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