Allegro A6595KLW, A6595KA Datasheet
6595
Data Sheet
26185.120
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
POWER
GROUND
SUPPLY
SERIAL
DATA IN
REGISTER
OUTPUT
ENABLE
POWER
GROUND
Note that the A6595KA (DIP) and the A6595KLW (SOIC)
are electrically identical and share a common terminal
number assignment.
LOGIC
OUT
OUT
OUT
OUT
CLEAR
1
2
V
DD
3
4
0
5
1
6
2
7
3
8
9
10
CLR
OE
LATCHES
REGISTER
LATCHES
REGISTER
ST
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO............................... 50 V
Output Drain Current,
Continuous, IO.......................... 250 mA*
Peak, IOM................................. 750 mA*†
Peak, IOM....................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS................................................. 75 mJ
Logic Supply Voltage, VDD.................. 7.0 V
Input Voltage Range,
VI................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD........................................... See Graph
Operating Temperature Range,
TA................................. -40°C to +125°C
Storage Temperature Range,
TS................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
20
19
18
17
16
15
14
13
12
11
POWER
GROUND
LOGIC
GROUND
SERIAL
DATA OUT
OUT
7
OUT
6
OUT
5
OUT
4
CLOCKCLK
STROBE
POWER
GROUND
Dwg. PP-029-13
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The A6595KA and A6595KLW combine an 8-bit CMOS shift
register and accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power
loads.
The serial-data input, CMOS shift register and latches allow direct
interfacing with microprocessor-based systems. Serial-data input rates
are over 5 MHz. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. Similar devices with reduced
r
are available as the A6A595.
DS(on)
The A6595 DMOS open-drain outputs are capable of sinking up to
750 mA. All of the output drivers are disabled (the DMOS sink drivers
turned off) by the OUTPUT ENABLE input high.
The A6595KA is furnished in a 20-pin dual in-line plastic package.
The A6595KLW is furnished in a wide-body, small-outline plastic
package (SOIC) with gull-wing leads. Copper lead frames, reduced
supply current requirements, and low on-state resistance allow both
devices to sink 150 mA from all outputs continuously, to ambient
temperatures over 85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 250 mA Output Current (all outputs simultaneously)
■ 1.3 Ω Typical
■ Low Power Consumption
■ Replacements for TPIC6595N and TPIC6595DW
Always order by complete part number:
Part Number Package R
A6595KA 20-pin DIP 55°C/W 25°C/W
A6595KLW 20-lead SOIC 70°C/W 17°C/W
r
DS(on)
θJA
R
θJC
6595
g
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
2.5
2.0
SUFFIX 'A', R = 55
1.5
1.0
SUFFIX 'LW
θ
J
A
', R = 70
θ
J
A
°C/W
°C/W
0.5
0
25
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
Dwg. GS-004A
FUNCTIONAL BLOCK DIAGRAM
REGISTER
CLEAR
(ACTIVE LOW)
CLOCK
LOGIC SYMBOL
9
12
8
13
3
G3
R
1D
C2
SRG8
C1
2
2
V
DD
Dw
4
5
6
7
14
15
16
17
18
. FP-043
LOGIC
SUPPLY
SERIAL
DATA IN
STROBE
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
SERIAL
DATA OUT
OUTPUT
ENABLE
(ACTIVE LOW)
LOGIC
GROUND
POWER
GROUND
OUT
0
OUT
N
POWER
GROUND
Dwg. FP-013-5
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
V
DD
IN
Dwg. EP-010-15
LOGIC INPUTS
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH............................ ≥ 0.85V
Low-level input voltage, VIL................................. ≤0.15V
DD
DD
OUT
Dwg. EP-063-3
DMOS POWER DRIVER OUTPUT
V
DD
OUT
Dwg. EP-063-2
SERIAL DATA OUT
TRUTH TABLE
Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Output
Input Input I0I1I
HHR
LLR
XR
0R1
0R1
0R1R2
XXX … XX X — R0R1R2…R6R
P0P1P2…P6P
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
... I6I7Output Strobe I0I1I2... I6I7Enable I0I1I2…I6I
2
…R5R
…R5R
…R6R
R
6
6
R
6
6
R
7
7
7
P
7
7
P0P1P2…P6P
LP0P1P2…P6P
7
XXX … XX H HHH … HH
7
7
Loading...