ALLEGRO A6285 User Manual

A6285

16-Channel Constant-Current Latched LED Driver

with Open LED Detection and Dot Correction

Features and Benefits

▪ 3.0 to 5.5 V logic supply range
▪ Schmitt trigger inputs for improved noise immunity
▪ Power-On Reset (POR)
▪ Up to 80 mA constant-current sinking outputs
▪ LED open circuit detection (LOD)
▪ Dot correction (DC) for adjusting LED light intensity on

each channel with 7-bit resolution

▪ Low-power CMOS logic and latches
▪ High data input rate up to 30 MHz
▪ Active output pull-ups with enable/disable
▪ 20 ns typical staggering delay between outputs
▪ Internal UVLO and thermal shutdown (TSD) circuitry
▪ Fault output flags for an LED open circuit (LOD) or a

thermal shutdown (TSD) condition

Package: 32 Contact QFN (suffix ET)

5 mm × 5 mm

0.90 mm nominal overall height

Description

The A6285 is designed for LED display applications. This
BiCMOS device includes an On/Off shift register, a Dot
Correction (DC) shift register, accompanying data latches, and
16 MOS constant-current sink drivers with active pull-ups that
can be enabled or disabled as required by the application.

The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A CMOS serial
data output permits cascading of multiple devices in applications
requiring additional drive lines.

Individual LED light intensity can be adjusted to correct for light
intensity variations by using the Dot Correction feature.

Open LED connections can be detected, and then signaled back
to the host microprocessor through the serial data output (SDO
pin). The FAULT output flags an LED open circuit (LOD)
condition or a thermal shutdown (TSD) condition. A staggering
delay on the load outputs during ON/OFF transitions helps to
reduce ground bounce.

Continued on the next page…

Not to scale

Controller

T ypical Application

V

DD

100 KΩ

SDI SDI
FAULT

CLK
LE
MODE
OE

SDO

FAULT

CLK

LE

MODE

OE

V

LED

PE

OUT0 OUT15

A6285

V

LED

10 μF

SDO

V

DD

100 nF

REXT

6285-DS, Rev. 1

16-Channel Constant-Current Latched LED Driver

A6285

with Open LED Detection and Dot Correction

Description (continued)

The device is available in a 32-lead QFN (package ET), with an
exposed thermal pad. It is lead (Pb) free with 100% matte tin
leadframe plating.

Selection Guide

Part Number Package Packing (estimated)

A6285EET-T 5×5 mm QFN, 32 pin, exposed thermal pad 73 pieces per tube

A6285EETTR-T 5×5 mm QFN, 32 pin, exposed thermal pad 1500 pieces per 7-in reel

Applications include the following:

▪ Display backlighting
▪ Monocolor, multicolor, or full-color LED display
▪ Monocolor, multicolor, LED Signboard
▪ Multicolor LED lighting

Absolute Maximum Ratings

Characteristic Symbol Notes Min. Max. Unit

Supply Voltage* V

OUTx Current (any single output) I

Input Voltage Range* V

LED Load Supply Range* V

ESD Rating

Operating Temperature Range (E) T

Junction Temperature T

Storage Temperature Range T

*With respect to ground (GND, PGND).

DD

O

VOE, VLE, V

I

LED

HBM (JEDEC JESD22-A114, Human Body Model) – 1.5 kV

CDM (JEDEC JESD22-C101, Charged Device Model) – 1.0 kV

A

(max) – 150 °C

J

stg

CLK

, V

SDI

, V

MODE

–0.3 5.5 V

–90mA

–0.3 VDD + 0.3 V

–0.3 13.2 V

–40 85 °C

–55 150 °C

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

2

A6285

16-Channel Constant-Current Latched LED Driver

with Open LED Detection and Dot Correction

Functional Block Diagram

MODE

CLK

SDI

OE

REXT

GND

LE

TSD

UVLO

01 15

1

MODE

0

1

MODE

0

1

ON/OFF Shift Register

0

MODE

015

1

0

MODE

ON/OFF
Register

0

LOD

0

Io

Regulator

LE

DC Register

06

7-Bit

DC

015

LOD

1

Status Info:

LOD

ON/OFF
Register

1

TSD
LOD

VDD

DC Shift Register

0 111

DC Register

713

7-Bit

DC

ON/OFF
Register

LOD

15

FAULT

UVLO

POR

1

0

DC Register

15

105 111

7-Bit

DC

VDD

SDO

MODE

PAD

PE

OUT0 OUT1

Inputs and Outputs Equivalent Circuits

(Note: Resistor values are equivalent resistance and not tested.)

VDD

CLK, SDI, LE,
MODE, O¯ ¯ E¯

500 Ω

10 Ω

10 Ω

VDD

SDO

FAULT

OUT15

Active Pull-up Cell

(1 of 16 Outputs)

5 mA

ON

VLED

PE

OUTx

V

LED

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

3

16-Channel Constant-Current Latched LED Driver

A6285

with Open LED Detection and Dot Correction

Pin-out Diagram

CLKLEOE

GND

VDD

REXT

MODE

FAULT

32313029282726

1

SDI

2

NC

3

OUT0

4

Terminal List Table

OUT1

PGND

OUT2

OUT3

OUT4

5

6

7

8

PAD

9

10111213141516

OUT5

OUT6

OUT7

PGND

Name Number Description

O¯ ¯E¯ 30

Output Enable input. Active low. When O¯ ¯E¯ = High, all OUTx outputs are forced OFF. When O¯ ¯E¯ = Low,
ON/OFF of OUTx outputs are controlled by input data.

GND 29 Logic supply ground.

PE 23

Active Pull-up Enable. When connected to LED Load Supply (V
= disabled.

REXT 27 Reference current input/output terminal.

MODE 26

Logic input, Mode select. When MODE = Low, then SDI, SDO, CLK, LE are connected to ON/OFF control

logic. When MODE = High, SDI, SDO, CLK, LE are connected to dot-correction logic.
NC 2 No connection. Not internally connected.
OUT0 3
OUT1 4
OUT2 6
OUT3 7
OUT4 8
OUT5 9
OUT6 11
OUT7 12
OUT8 13

Constant current outputs.

OUT9 14
OUT10 16
OUT11 17
OUT12 18
OUT13 19
OUT14 21
OUT15 22

PGND 5, 10, 15, 20 Power ground.

CLK 32

Data shift clock input. Note that the internal connections are switched by input at MODE pin. At CLK, the

shift-registers selected by MODE shift the data.
SDI 1 Serial Data In. Data input of serial data interface.
SDO 24 Serial Data Out. Data output of serial data interface.
VDD 28 Logic Supply.
FAULT 25 Error output. FAULT is open drain terminal. FAULT goes low when LOD or TSD detected.

LE 31

Latch Enable input. Note that the internal connections are switched by input at the MODE pin. At LE, the

latches selected by MODE get new data.

PAD – Exposed pad for enhanced thermal dissipation; not connected internally, connect to power ground plane.

OUT8

OUT9

25

PGND

24

23

22

21

20

19

18

17

OUT10

SDO

PE

OUT15

OUT14

PGND

OUT13

OUT12

OUT11

) = enabled, when connected to PGND

LED

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

4