Allegro A6259KLW, A6259KA Datasheet
6259
Data Sheet
26186.120
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
POWER
GROUND
SUPPLY
S (LSB)
GROUND
POWER
GROUND
LOGIC
0
OUT
OUT
OUT
OUT
LOGIC
1
2
V
DD
3
4
0
5
1
6
2
7
3
8
S
1
9
10
LATCHES
DECODER LOGIC
LATCHES
EN
Note that the A6259KA (DIP) and the A6259KLW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T
= 25°C
A
Output Voltage, VO............................ 50 V
Output Drain Current,
Continuous, IO...................... 250 mA*
Peak, IOM............................. 750 mA*†
Peak, IOM................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS............................................. 75 mJ
Logic Supply Voltage, VDD.............. 7.0 V
Input Voltage Range,
VI............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD....................................... See Graph
Operating Temperature Range,
T
............................. -40°C to +125°C
A
Storage Temperature Range,
T
............................. -55°C to +150°C
S
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
POWER
GROUND
19
CLEAR
1820DATA
OUT
17
OUT
16
OUT
15
14
OUT
ENABLE
13
S (MSB)
12
2
11
POWER
GROUND
Dwg. PP-050-2
7
6
5
4
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6259KA and A6259KLW combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pullup resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6259KA/KLW
DMOS open-drain outputs are capable of sinking up to 750 mA. Similar
devices with reduced r
The A6259KA is furnished in a 20-pin dual in-line plastic package.
The A6259KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applications. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 250 mA Output Current (all outputs simultaneously)
■ 1.3 Ω Typical
■ Low Power Consumption
■ Replacements for TPIC6259N and TPIC6259DW
Always order by complete part number:
Part Number Package R
A6259KA 20-pin DIP 55°C/W 25°C/W
A6259KLW 20-lead SOIC 70°C/W 17°C/W
r
DS(on)
are available as the A6A259.
DS(on)
θJA
R
θJC
6259
g
8-BIT ADDRESSABLE
DMOS POWER DRIVER
2.5
2.0
S
U
F
F
IX
'A
', R
θJA
=
θJA
5
5
°C/W
°C
/W
1.5
1.0
SUFFIX 'LW', R = 70
0.5
0
25
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
V
DD
IN
Dwg. GS-004A
LOGIC SYMBOL
3
8
12
13
18
19
0
2
G8
Z9
Z10
9,0D
10,0R
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
8M 0/7
Dw
4
5
6
7
14
15
16
17
. FP-046
OUT
Dwg. EP-010-15
FUNCTION TABLE
Inputs
CLEAR ENABLE DATA OUTPUT OUTPUTs Function
HLH L R
HLL H R
H H X R R Memory
LLH L H
LLL H H
L H X H H Clear
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
Addressed Other
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
DMOS POWER DRIVER OUTPUTLOGIC INPUTS
Addressable
Latch
8-Line
Demultiplexer
Dwg. EP-063
LATCH SELECTION TABLE
Select Inputs
S2 (MSB)S1S0 (LSB) OUTPUT
LLL 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7
Addressed
FUNCTIONAL BLOCK DIAGRAM
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
(LSB)
(MSB)
S
0
S
1
S
2
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
OUT
OUT
OUT
OUT
OUT
0
1
2
3
4
LOGIC
SUPPLY
LOGIC
GROUND
DATA
ENABLE
(ACTIVE LOW)
CLEAR
(ACTIVE LOW)
www.allegromicro.com
D
V
DD
C1
CLR
D
C1
CLR
D
C1
CLR
Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.
OUT
5
OUT
6
OUT
7
POWER
GROUND
Dwg. FP-047-1
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