ALLEGRO A4490 User Manual

A4490

T riple Output Step-Down Switching Regulator

Features and Benefits

▪ Three buck converters
▪ 4.5 to 34 V input voltage range
▪ 550 kHz fixed frequency
▪ Multiphase switching
▪ Independent control of each converter
▪ Power-on-reset flag
▪ Internal compensation
▪ 4 × 4 mm QFN Package, small PCB footprint

Package: 20-contact QFN (suffix ES)

Description

Designed to provide the power supply requirements of printers,
office automation, industrial, and portable equipment, the
A4490 provides three high current, high performance, switching
regulator outputs with independent soft start.

High frequency switching allows selection of inexpensive
inductors and small ceramic output capacitors. The turn-on
cycles of the regulators are interleaved to minimize stresses on
the input capacitors and to reduce EMI. A charge pump is used
to provide the supply for driving the power switches, ensuring
operation at very wide operating duty cycles and avoiding the
need for power-draining clamp circuits.

A power-on-reset circuit with user configurable delay indicates
when enabled regulators are in specification. The power-on­reset flag also indicates when the input voltage drops below
specification, giving the system controller advance warning
while the switchers continue to operate down to the shutdown
level.

Internal diagnostics provide comprehensive protection against
overloads, input undervoltages, and overtemperatures.

Continued on the next page…

Approximate size

Microcontroller or
Controller Logic

Typical Application

V

BB

VDD

CP1 CP2 VCP

PORZ

CPOR

A4490

ENB1

ENB2

ENB3

PGND

GND

VBB1

LX1

FB1

VBB2

LX2

FB2

VBB3

LX3

FB3

V

V

V

REG1

REG2

REG3

4490-DS, Rev. 6

A4490

T riple Output Step-Down Switching Regulator

Description (continued)

The A4490 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm
nominal overall height QFN, with exposed pad for enhanced thermal
dissipation. It is lead (Pb) free, with 100% matte tin leadframe
plating.

Applications include the following:

▪ Photo, inkjet, and portable printers
▪ Industrial
▪ Hand-held devices
▪ Portable applications

Selection Guide

Part Number Packing

A4490EES-T 92 pieces per tube
A4490EESTR-T 1500 pieces per 7-in. reel

Operating Temperature Range

(°C)

–40 to 85

Absolute Maximum Ratings (reference to GND)

Characteristic Symbol Notes Rating Units

Load Supply Voltage V

LX1, LX2, and LX3 Pins V

PORZ and VDD Pins V

ENBx Pin Input Current I

Operating Ambient Temperature T

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature T

BB

LXn

IN

ENBx

A

stg

Driven by a current-limited voltage source 1 mA

Range E –40 to 85 ºC

36 V

–1 to 36 V

–0.3 to 7 V

–55 to 150 ºC

Recommended Operating Conditions

Characteristic Symbol Conditions Min. Typ. Max. Units

Load Supply Voltage V

LX1, LX2, and LX3 Pins V

Operating Ambient Temperature T

Junction Temperature T

BB

LXn

A

J

To operate at VBB < 6 V, connect VDD
supply to the VBB supply. See Powering
Configurations section.

4.5 – 34 V

–0.7 – 34 V

–40 – 85 ºC

–40 – 125 ºC

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance

*Additional thermal information available on the Allegro website.

R

θJA

On 4-layer PCB based on JEDEC standard 37 ºC/W

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

2

A4490

T riple Output Step-Down Switching Regulator

Functional Block Diagram

C2

47 nF

CP1

V

BB

CP2

V

BB

100 nF

100 kΩ

470 nF

V

C14

C1

DD

VDD

ENB1

ENB2

PORZ

CPOR

ENB3

PGND

Regulator

Switch

Bias Supply

SS

SS

POR Block

SS

Switcher #1

PWM Control

Switcher #2

PWM Control

Switcher #3

PWM Control

Charge Pump

VCP

VCP

VCP

VCP

VBB1

LX1

FB1

VBB2

LX2

FB2

VBB3

LX3

FB3

GND

C3

47 nF

C4

L1

D1

15 μH

L2

D2

D3

10 μH

L3

4.7 μH

10 μF

C5

10 μF

R1

R2

C6

10 μF

C7

10 μF

R3

R4

C9

10 μF

C10

10 μF

R5

R6

V

3.3 V / 1.5 A

C8

10 μF

C11

10 μF

V

REG1

5 V / 1.5 A

REG2

C12

10 μF

V

REG3

1.0 V / 1.5 A

C13

10 μF

V

BB

Note: All capacitors ceramic X5R.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

3

A4490

T riple Output Step-Down Switching Regulator

Pin-out Diagram

ENB1

LX1

VBB1

VBB3

LX3

2019181716

10

VCP

ENB3

15

FB3

14

PGND

13

CP1

12

CP2

11

FB1

1

VDD

2

GND

FB2

ENB2

3

4

5

PAD

678

LX2

VBB2

CPOR

9

PORZ

Terminal List

Number Name Function

1 FB1 Feedback REG1

2 VDD Bias supply

3 GND

4 FB2 Feedback REG2

5 ENB2 Enable REG2, logic input, active high

6 LX2 Switch node REG2

7 VBB2

8 CPOR POR delay adjustment

9 PORZ Power on reset output, active low

10 VCP Charge pump reservoir

11 CP2 Charge pump capacitor terminal

12 CP1 Charge pump capacitor terminal

13 PGND

14 FB3 Feedback REG3

15 ENB3 Enable REG3, logic input, active high

16 LX3 Switch node REG3

17 VBB3

18 VBB12 Input supply for REG1

19 LX1 Switch node REG1

20 ENB1 Enable REG1, logic input, active high

–PAD

1

GND and PGND should be connected externally.

2

The three VBBx pins should be connected together externally.

3

Thermal pad should be connected to the ground (0 V) plane using thermal vias.

1

Ground

2

Input supply for REG2

1

Ground for charge pump circuitry

2

Input supply for REG3

3

Exposed pad for enhanced thermal dissipation

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

4

A4490

T riple Output Step-Down Switching Regulator

ELECTRICAL CHARACTERISTICS

1,2

at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units

General

VBB Quiescent Current

I

I

BBOFF

VDD Supply Range V

VDD Quiescent Current I

BBON

current drawn by feedback resistors ignored

ENBx = high, I

ENBx = 0 V – 1 – μA

3.3 – 5.5 V

DD

ENBx = high – – 5 mA

DD

ENBx = 0 V – 1 – μA

= 0 mA, VBB = 12 V,

LOAD

– 1 2 mA

REG1, REG2, and REG3

Feedback Input Bias Current I

Feedback Voltage V

Output Voltage Regulation

3

–400 –100 100 nA

BIAS

FB

V

OUT

With respect to 0.8 V target voltage – ±1.5 – %

V

= 5 V, I

REGx

V

= 5 V, I

REGx

= 0 to 1.5 A, TA = –20°C to 85°C –2.5 – 2.5 %

OUT

= 0 to 1.5 A, TA = –40°C to 85°C –3.5 – 3.5 %

OUT

PWM Frequency fSW 470 550 630 kHz

Maximum Duty Cycle DC

Minimum Duty Cycle DC

Buck Switch On-Resistance R

Current Limit Threshold I

90 – – %

max

– 5 – %

min

TJ = 25°C, I

TJ = 125°C, I

DS(on)

TJ = 25°C, I

TJ = 125°C, I

Peak current through switch with D = 0.9 2.0 A

LIM

= 1.5 A, VBB = 6.0 V – 450 – mΩ

LOAD

= 1.5 A, VBB = 6.0 V – 700 – mΩ

LOAD

= 1.5 A, VBB = 4.5 V – 560 – mΩ

LOAD

= 1.5 A, VBB = 4.5 V – 870 – mΩ

LOAD

Soft Start Duration tss 0.625 1.25 1.875 ms

Logic Inputs and Outputs

ENBx Input Voltage

ENBx Input Hysteresis V

VIL – – 0.8 V

VIH 2.0 – – V

I(hys)

300 500 – mV

ENBx Input Current IIL VIH ≤ 5 V –1 – 1 μA

PORZ Output (Open Drain) V

PORZ Output Leakage Current I

PORZL

PORZH

I

PORZL

V

PORZ

= 1 mA, fault asserted – – 0.4 V

= 5 V, fault not asserted –1 – 1 μA

Continued on the next page…

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

5

A4490

T riple Output Step-Down Switching Regulator

ELECTRICAL CHARACTERISTICS

1,2

(continued) at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Power-On Reset Duration t

C

POR

= 470 nF 75 115 155 ms

POR

Protection

VREGx Undervoltage Lockout Startup V

VREGx Undervoltage Lockout Shutdown V

VREGx Undervoltage Lockout
Startup Hysteresis

VBB Undervoltage Lockout Startup

VBB Undervoltage Lockout Shutdown

VBB Undervoltage Lockout
Shutdown Hysteresis

VBB Undervoltage Warning Threshold V

REGUV(su)

REGUV(sd)

V

REGUV(suhys)

V

V

BBCPUV(su)

V

V

BBCPUV(sd)

V

BBUV(sdhys)

V

BBCPUV(sdhys)

BBUV(por)

Junction Overtemperature Shutdown T

Junction Overtemperature Shutdown
Hysteresis

1

For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin.

2

Specifications over the junction temperature range of –40°C to 125°C are assured by design and characterization.

3

Average value of V

relative to target voltage. The effects of the feedback resistors are not taken into account.

OUT

T

JTSD(hys)

FB1, FB2, and FB3 rising – 85 – %VFB

FB1, FB2, and FB3 falling – 80 – %VFB

No external VDD supply, VBB rising 3.9 4.3 4.6 V

BBUV(su)

External VDD supply, VBB rising 3.9 4.2 4.4 V

No external VDD supply, VBB falling 3.7 4.1 4.5 V

BBUV(sd)

External VDD supply, VBB falling 3.0 3.5 4.1 V

No external VDD supply – 500 – mV

External VDD supply – 600 – mV

VBB falling (forces PORZ low); switchers continue
to operate

Temperature rising – 165 – °C

JTSD

Recovery = T

JTSD

–T

– 15 – °C

JTSD(hys)

–5 –%

– 3.6 – V

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

6

A4490

T riple Output Step-Down Switching Regulator

Functional Description

Basic Operation

The A4490 contains three fixed frequency, buck switching con­verters with peak current-mode control, including slope compen­sation. Each converter can be independently turned on and off via
the enable inputs (EN1, EN2, and EN3), which are active high.
When enabled, the corresponding output is brought-up under the
control of a soft start routine, which avoids output voltage over­shoot and minimizes input inrush current.

The output voltage is typically divided down by an external
potential divider, and is compared against an internal reference

voltage to produce an error signal, also known as the current
demand signal. The current signal through the buck switch is

converted into a voltage. This signal is then compared against the
current demand signal to create the required duty cycle.

At the beginning of each switching cycle, the buck switch is
turned on. When the current signal through the switch reaches the
level of the current demand signal, the on-time of the switch is
terminated. On the next switching cycle, the switch is turned on
again and the cycle is repeated.

One shared clock is used to define the switching frequency for
each regulator. Each of the three switching cycles (REG1, REG2,
and REG3) are phase shifted with respect to one another by 120°
in an attempt to minimize the pulsed current drawn from the
input filter capacitors. Under certain conditions, for example at
low V

conditions and relatively high user-set output voltages,

BB

switching overlap between channels is inevitable.

Under conditions, such as light loads or high VBB voltages, that
cause duty cycles (DC) of less than the minimum value, the
converter enters a pulse-skipping mode to ensure regulation is
maintained.

A charge pump regulator is provided to ensure a sufficient gate
drive is available for all three power switches across the full input
voltage range. This regulator allows operation even at very wide
operating duty cycles. On initial power-up, an internal regulator
is used to provide the bias supply for on-chip control functions.

Each regulator channel utilizes pulse-by-pulse current limiting in
the event of either a short circuit or an overload. If the overload
is applied long enough, the IC temperature may rise sufficiently
to cause the thermal shutdown circuit to operate. The part will

auto-restart under control of the soft start circuit after the thermal
disable condition is removed, and assuming all other conditions
are met. See the Shutdown section for more information.

Power Configuration

The A4490 supports alternative schemes for providing logic sup­ply voltage on the VDD pin. In addition, the IC can be powered
up and down using either the VBB or ENB pins.

Powering VDD To minimize power dissipation, especially at
high input voltages, it is recommended that an external sup­ply be applied to the VDD input pin. Typically, this voltage is
derived from one of the three regulated outputs that are set-up for
between 3.3 and 5 V (V

REGx

).

Another advantage of powering the VDD externally is that the
VBB undervoltage lockout level is lowered. To maximize the
run time of the switchers during a VBB power-down condition,
two alternative undervoltage shutdown conditions are supported,
depending on which VDD-powering configuration has been
implemented. When no external VDD is applied, the minimum

, V

V

BB

BBUV(sd) ,

applied, the minimum VBB, V

is 4.2 V typical. When an external VDD is

BBCPUV(sd)

, is 3.4 V typical.

One note of caution when deriving VDD from a VREG output:
during initial application of VBB, the internal bias supply auto­matically starts from the internal regulator because VREG has not
yet reached regulation. This means the startup threshold is deter­mined by V

BBUV(su)

(4.3 V typical) because there is no external
VDD. When VREG has begun to supply VDD externally, the
shutdown threshold reduces to V
assumes that V

is present.

REG

BBCPUV(sd)

(3.4 V typical). This

Powering Up and Down with VBB Referring to figure 1,
each of the enable inputs (ENBx) are held high by being tied to
the VBB rail via a 100 kΩ resistor and the VDD is supplied from
one of the regulator outputs. When the VBB voltage reaches the
minimum threshold, V
ramps up. When V
old V

BBCPUV(su)

BB

, the soft start routines are initiated (tSS) for all

BBUV(su)

+ VCP has reached the minimum thresh-

, the charge pump supply (VCP)

three regulator channels (VREGx). When all three regulators
have reached the 85% FBx threshold, the power-on-reset timer
is initiated. After the power-on-reset period, t

, has elapsed,

POR

PORZ goes high, indicating that all the regulators and VBB are in
specification.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

7

A4490

VBB

0V

VBB+VCP

T riple Output Step-Down Switching Regulator

V

BBUV(su)

V

BBCPUV(su)

V

BBUV(por)

V

BB

+5.5 V

V

BBCPUV(sd)

VREG1

85%FB1

VREG2

VREG3

PORZ

t

85%FB2

85%FB3

t

SS

POR

Figure 1. Timing diagram for powering up and down using the VBB pin

VBB

0V

ENB1

ENB2

ENB3

VREG1
VREG2
VREG3

PORZ

t

SS

t

SS

85%FB1

85%FB2

t

POR

80%FB2 85%FB2

85%FB3

t

SS

t

POR

Figure 2. Timing diagram for powering up and down using the ENB pin

t

POR

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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

8

A4490

T riple Output Step-Down Switching Regulator

When the VBB voltage starts to fall below the undervoltage warn­ing level, V

BBUV(por)

, of 3.6 V typical, the PORZ flag resets.
This gives advance warning to the system controller that the VBB
voltage is falling. Note that this feature is only guaranteed when
VDD is supplied externally. During this interval, the three switch­ers continue to operate.

While V

falls further, the VCP supply also tends to fall, which

BB

degrades the drive voltage to the series switches. In addition,
the higher voltage rails start to fall out of regulation first, as the
corresponding maximum duty cycle (D

) for these particular

max

converters is reached.

The regulators that have the lower output voltages achieve some
level of steady state, before the A4490 powers down when all
of the corresponding VBB undervoltage thresholds have been
reached. For example, it may be possible for a 1 V output to
continue to operate down to a V

of 3.4 V typical, if the VDD

BB

supply is derived externally. The extent of this effect depends on
a myriad of factors, including input and output filter capacitance,
output loads, gate drive amplitude, MOSFET R

DS(on)

, and so

forth.

Powering Up and Down with Enable Referring to figure 2,
VBB is present and the UVLO start-up thresholds, V
and V

BBCPUV(su)

have been reached. Each of the regulators are

BBUV(su)

enabled in turn. Initially, VREG1 is enabled and is brought-up
under the control of the soft start circuit (t

). Before VREG1

SS

reaches 85% FB1, VREG2 is enabled and is brought-up under a
separate soft start control.

When both regulators have reached their respective 85% FB
thresholds, the power-on-reset (POR) timer is initiated. Note that
the POR timer is only enabled after all of the enabled regulators
reach their corresponding 85% FB levels. After the power-on­reset time, t

, has elapsed, if the FB levels of VREG1 and

POR

VREG2 are not below their respective 80% FB levels, then the
PORZ signal will go high.

At some point later, if VREG3 is enabled, then the PORZ is
reset and VREG3 is brought-up under the control of the soft start
circuit. When the 85% FB3 threshold is reached, the POR timer
is initiated. After t

has elapsed, if all the FB levels are above

POR

their respective 80% FB levels, then the PORZ signal will go
high.

Note that if any regulator channel is not enabled, the channel
will not influence PORZ. To avoid multiple signal changes of the

PORZ signal, it is recommended that the system be designed such
that all three regulator channels are within specification before
t

has elapsed.

POR

If any regulator channel drops below 80% FB, the PORZ signal
will be reset. If the voltage then recovers to within 85% FB, the
POR timer is initiated again. Note that a soft start is not initiated
when the feedback voltage drops below the 80% FB level. This is
to allow a rapid auto-restart in the event of an overload or similar
fault. If a soft start is required, it is recommended that on receipt
of the PORZ reset signal, the system controller disables and then
re-enables the relevant regulator channels again. As soon as the
last regulator is disabled the PORZ signal is reset.

Power on Reset The power-on-reset duration, t

POR

, is deter­mined by selecting an appropriate capacitor connected to the
CPOR pin. The value of t

can be determined by the following

POR

formula:

t

= 2.131 ×10

POR

5

× C

. (1)

POR

The PORZ output goes high when both VBB is above the under­voltage warning levels, and the FB pins of the regulators that are
enabled are > 85% of the V

REG

voltage.

Because the external capacitor is charged via a 5 μA current
source, care must be taken in the layout to avoid additional leak­age paths. The capacitor should be positioned adjacent to the
CPOR pin, and the ground connection to the A4490 GND pin
should be as short as possible.

It is recommended that the t

period be set to exceed the

POR

start-up phases of all three regulators, to avoid the possibility of
multiple triggerings of the PORZ output.

Output Voltage Selection The output voltage on each of the
three regulators is set by the following relationship, shown here
for the VREG1 channel:

⎛

V

REG1

R1R

⎜

=,

2

⎜

V

FB

⎝

– 1

⎞
⎟

⎟
⎠

(2)

where R2 (connected between GND and the FB1 pin) should
be a value between 4.7 and 12 kΩ. R1 is connected between the
output rail and the FB1 pin. V

is the set output regulator

REG1

voltage. VFB is the reference voltage.

The tolerances of the feedback resistors influence the voltage set­point. It is therefore important to consider the tolerance selection
when targeting an overall regulation figure.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

9

A4490

T riple Output Step-Down Switching Regulator

The bias current, I

, flowing out of the FB1 node into R2, will

BIAS

introduce a small voltage offset to the output.

Enable Each regulator channel can be individually enabled via
the corresponding ENBx pin. If any channel is required to start­up automatically after the VBB voltage is applied, that particu­lar channel should have the ENB pin tied to the VBB rail via a
pull up resistor.

This resistor should be selected to limit the current to less than
the maximum specified value, 1 mA. This prevents the internal
protection clamps from turning on. It is recommended that a
100 kΩ pull-up resistor be used. This would ensure the current
remains below the maximum value when V

= 36 V.

BB

Soft Start Each regulator channel contains a soft start circuit. A
soft start cycle is initiated when the appropriate regulator enable
input is set to high; the VBB, charge pump, and bias supply volt­ages are above the minimum values; and no thermal shutdown
condition exists. Note that an overload or short circuit will not
cause a soft start cycle, unless a thermal shutdown event occurs.

During a soft start cycle, the reference voltage is ramped from
0 to 0.8 V typical, which in turn forces the current demand signal
to increase in a linear fashion.

Shutdown All converter channels are disabled in the event of
either a thermal shutdown event or an undervoltage on VBB
(V

BBUV(sd)

or V

BBCPUV(sd)

).

As soon as the above fault conditions have been removed, and
assuming the ENB inputs are enabled, the appropriate channels
will auto-restart under control of the soft start.

Current Limit The typical peak current limit for each channel is
specified as 2.5 A minimum, with a duty cycle of 0.9. The mini­mum current limit occurs at maximum duty cycle (0.9), because
the slope compensation has a maximum effect under this condi­tion. As the duty cycle reduces, the current limit increases. This
means for applications that operate with a narrow duty cycle, it is
possible to operate with a load current greater than 2.0 A.

Figure 3 illustrates the typical peak current limit versus duty
cycle. For example, it is possible to operate with a peak current
limit of 3.75 A with a duty cycle of 0.3.

to check the implications on the thermal performance. See the
Thermal Considerations section.

Component Selection

Inductor The inductance value, L, determines the ripple current.

It is important to ensure that the minimum current limit is not
exceeded under worst-case conditions: VBB(min), I

LOAD

(max),

fSW(min), and L(min).

It is recommended that gapped ferrite solutions be used as
opposed to powdered iron solutions, the latter of which exhibit
relatively high core losses that can have a large impact on long
term reliability.

Inductors are typically specified at two current levels, rms cur­rent and saturation current. With regard to the rms current, it is
important to understand how the rms current level is specified,
in terms of ambient temperature. Some manufacturers quote an
ambient only, whilst others quote a temperature that includes a
self-induced temperature rise. For example, if an inductor is rated
for 85°C and includes a self-induced temperature rise of 25°C
at maximum load, then the inductor cannot be safely operated
beyond an ambient temperature of 60°C at full load. The rms cur­rent can be assumed to be simply the maximum load current, with
perhaps some margin to allow for overloads, and so forth.

The first stage of determining the inductor value is to specify a
peak-to-peak ripple current of typically about 20% to 25% of the
maximum load.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

0.5

Current Limit (A)

1.0

0.5
0

020406080100

Duty Cycle (%)

As well as ensuring the peak current limit is not exceeded, under
worst case load and input voltage conditions, it is also important

Figure 3. Current limit versus duty cycle

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

10

A4490

T riple Output Step-Down Switching Regulator

The maximum peak-to-peak ripple current, I

, occurs at the

RIPPLE

maximum input voltage. Therefore the duty cycle, D, should be

found under these conditions (for the VREG1 channel):

V

D(min)

REG1+Vf

=

VBB(max)+V

.

f

(3)

where Vf is the forward voltage drop of the recirculation diode.

The required inductance can be found:

f

SW

1

(min)

,

(4)

L

(min)

VBB(max) – V

=

I

RIPPLE

REG1

××

D(min)

Note that the manufacturers inductance tolerance should also

be taken into account. This value may be as high as ±20%. The

peak-to-peak current should not exceed 1 A, to avoid instability

in the innermost circuit loops due to insufficient slope compensa-

tion.

The maximum peak current can be found from to ensure that the

saturation current level of the chosen inductor is not exceeded:

I

=

I

I

sat

LOAD

+

RIPPLE

2

.

(5)

Recommended inductor manufacturers and ranges are:

• Taiyo Yuden: NR6045 series for 1.5 A outputs

• Taiyo Yuden: NRG4026 series for 1.0 A outputs

• Sumida: CDH74 series for 1.5 A outputs

Output Capacitor In the interests of size, cost and perfor-

mance, it is highly recommended that ceramic X5R or X7R

capacitor types be used. When using ceramic capacitors another

important consideration is the E-field effects on the actual value

of the capacitor. To minimize the effects of the capacitance

reducing with output voltage, it is recommended that the working

voltage of the capacitor be considerably more than the set output

voltage. As a suggestion, it is recommended that 6.3 V-rated

capacitors should be used for output voltages of 3.3 V and below.

For output voltages of 5 V, a 10 V-rated capacitor should be used.

The output capacitor determines the output voltage ripple and is
used to close the control loop. To guarantee stability, the capaci­tance has to increase as the output voltage is reduced. This is
actually reasonable from a ripple voltage point of view, as the
ripple voltage is typically specified as a percentage of output
voltage.

The following table outlines what the minimum output capaci­tance should be for a given output voltage:

Output Voltage

(V)

510

3.3 20

1.8 to 2.5 30

<1.8 40

Minimum Output Capacitance

(μF)

Capacitance values with greater than the above values can be
used with the effect of reducing the bandwidth. This may be nec­essary in systems that have extremely low ripple/noise require­ments.

The output ripple is largely determined by the output capacitance
and the effects of ESR and ESL can largely be ignored assuming
good layout practice is observed.

The output voltage ripple can be approximated to:

I

RIPPLE

≈

8 × fSW × C

OUT

V

RIPPLE

,

(6)

When using ceramic capacitors, there is generally no need to con­sider the current carrying capability due to the negligible heating
effects of the ESR. Also, the rms current flowing into the output
capacitor is extremely low.

Input Capacitor Again it is highly recommended that ceramic,
X5R or X7R capacitors be used.

The value of the input capacitance determines the amount of
current ripple (EMI) that appears at the source (VBB supply)
terminals. The amounts of current flowing in and out of the input
capacitor depend on the relative impedances between the input
capacitor impedance and the source impedance. To achieve a low
impedance filter solution it is recommended to place at least two
capacitors in parallel.

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115 Northeast Cutoff
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11

A4490

T riple Output Step-Down Switching Regulator

Again, there is generally no need to consider the heating effects
of the rms current flowing through the ESR. Also, the phase­shifting of the input current drawn by each of the regulators helps
to reduce the overall rms current.

Flyback Diode This diode conducts during the switch off-time.
A Schottky diode is recommended to minimize both the forward
drop and switching losses.

The worst case dissipation occurs at maximum V

, when the

BB

duty cycle, D, is a minimum. The average current through the
diode can be found:

I

DIODE(av)

= I

× (1 – D(min)) . (7)

LOAD

The forward voltage drop, Vf , can be found from the diode
characteristics by using the actual load current (not the average
current).

The static power dissipation can be found:

P

STAT

= I

LOAD(av)

× V

. (8)

f

It is also important to take into account the thermal rating of
the package, R

, and the ambient temperature, to ensure that

θJA

enough heatsinking is provided to maintain the diode junction
temperature within the safe operating area for the device.

The following steps can be used as a guideline for determining a
suitable thermal solution. It should be noted that this process is
usually an iterative one to achieve the optimum solution. These
factors can be considered as follows:

Step 1. Estimate the maximum ambient temperature, T

(max) , of

A

the application.

Step 2. Define the maximum junction temperature, TJ(max). Note
that the absolute maximum is 150°C.

Step 3. Determine the worst case power dissipation, PD(max).

The evaluation should consider these at maximum load and mini­mum VBB. Contributors are switch static and dynamic losses, and
control losses. These are described in the following sections

Switch Static Losses The following steps can be used to
determine switch static losses:

Estimate the maximum duty cycle:

V

+ V

D(max)

REG

=

VBB(min) + V

f

f

,

(9)

where Vf is the forward voltage drop of the Schottky diode under
the given load current.

To minimize the heating effects from the A4490 on the diode and
vice-versa, it is recommended that the diode be mounted on the
reverse side of the printed circuit board.

Support Components POR capacitor (C11), charge pump
capacitor (C1), reservoir capacitor (C2) and VDD filter capacitor
(C12) should be ceramic X5R or X7R.

Thermal Considerations

To ensure the A4490 operates in the safe operating area, which
effectively means restricting the junction temperature to less than
150°C, several checks should be made. The general approach
is to work out what thermal impedance (R

) is required to

θJA

maintain the junction temperature at a given level, for a particular
power dissipation.

Another factor worth considering is that other power dissipating
components on the system PCB may influence the thermal per­formance of the A4490. For example, the power loss contribution
from the recirculation diode and the sense resistor may cause the
junction temperature of the A4490 to be higher than expected.

Estimate the R

of the each regulator switch at the given

DS(on)

junction temperature:

⎛

T

⎜

R

DS(on)TJRDS(on)25C

=

1+

⎜
⎝

– 25

J

200

⎞
⎟

.

⎟
⎠

(10)

Note that if the VBB range is restricted to between 4.5 and 5.5 V,
the R

increases. For example, the R

DS(on)

at 25°C with a

DS(on)

VBB greater than 6 V is 450 mΩ typical, as stated in the Electri­cal Characteristics table. Under the same temperature conditions,
with the VBB = 4.5 V, the R
voltages between 4.5 and 6 V, the R

is 560 mΩ typical. For VBB

DS(on)

can be found by linear

DS(on)

approximation. For more information on operating the A4490
between a VBB voltage of 4.5 and 5.5 V, see the Power Configu­rations section.

The static loss for each switch can be determined:

P

where I

LOAD

= I

STAT

is the load for that particular regulator channel.

2

× D(max) × R

LOAD

DS(on)TJ

, (11)

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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

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12

A4490

T riple Output Step-Down Switching Regulator

Switch Dynamic Losses The following can be used to deter-

mine switch dynamic losses:

Both turn on and turn off losses can be estimated:

I

=

P

V

BB

(min)

DYN

LOAD

2

30 10

–9

f

SW

(12)

,

where fSW is the switching frequency.

Control Losses The following steps can be used to determine

control losses:

P

where I

is the quiescent current assuming all three regulators

BBON

VBB

= I

BBON

× V

, (13)

BB

are on.

P
where I

and is the quiescent current on VDD.

VDD

VDD

= I

VDD

× V

, (14)

DD

Total Losses The total losses can now be estimated:

P

+PDYN1

+P

TOTAL

= P

STAT1

VBB

+ P
+P

+ P

+ P

STAT2

DYN2

VDD

STAT2

+ P

DYN3

. (15)

Thermal Impedance The thermal impedance required for the

solution can now be determined:

TJ– T

A

=

R

QJA

P

TOTAL

.

(16)

Example

Selected parameters:

VBB(min) = 6 V

V

= 5 V at 1 A

REG1

V

= 3.3 V at 1 A

REG2

V

= 1.8 V at 800 mA

REG3

TA= 70°C

TJ = 115°C

Vf = 0.4 V

(a) Switch static losses

V

V

V

The R

R

DS(on)TJ

duty cycle, D

REG1

duty cycle, D

REG2

duty cycle, D

REG3

of each switch can be found:

DS(on)

450×10

=

==

1

==

2

==

3

–3

5+0.4
6+0.4

3.3+0.4
6+0.4

1.8+0.4
6+0.4

⎛
⎜

1+

⎜
⎝

115 – 25

200

0.84

0.58

0.34

⎞
⎟

0.653 Ω

=

⎟
⎠

The static loss of each switch can be found:

P

P
P

= 12 × 0.84 × 0.653 = 0.55 W

STAT1

= 12 × 0.58 × 0.653 = 0.379 W

STAT2

= 0.82 × 0.34 × 0.653 = 0.14 W

STAT3

(b) Switch dynamic losses

P

DYN1

P

DYN2

P

DYN3

1

6

==

2
1

6

==

2

0.8

6

==

2

30 10

30 10

30 10

–9

–9

–9

500 10

500 10

500 10

3

3

3

0.045 W

0.045 W

0.036 W

(c) Control losses
P

P

= 0.005 × 6 = 0.03 W

VBB

= 0.001 × 3.3 = 0.003 W

VDD

(d) The total power dissipation can now be found:
P

= 0.55 + 0.379 + 0.14 + 0.045

TOTAL

+ 0.045 + 0.036 + 0.03 + 0.003 = 1.228 W

(e) The thermal impedance required for the solution can be
found:

115

– 70

==

R

QJA

1.228

36.6 °C/W

For this particular solution a high thermal efficiency board is
required to ensure the junction temperature is kept below 115°C.
For maximum effectiveness, the PCB pad area underneath the
thermal pad of the A4490 should be exposed copper. Several
thermal vias (say between 4 and 8) should be used to connect
the thermal pad to the internal ground plane. If possible, an
additional thermal copper plane should be applied to the bottom
side of the PCB and connected to the thermal pad of the A4490
through the vias.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

13

A4490

p

T riple Output Step-Down Switching Regulator

This calculation assumes no thermal influence from other compo­nents. If possible, it is advisable to mount the flyback diodes on
the reverse side of the printed circuit board. Ensure low imped­ance electrical connections are implemented between board
layers.

PCB Layout Guidelines The ground plane is largely dictated
by the thermal requirements described in the previous section.
The ground referenced power components should be referenced
to a star ground, located away from the A4490 to minimize
ground bounce issues.

A small, local, relatively quiet ground plane near the A4490 should
be used for the ground referenced support components, to mini­mize interference effects of ground noise from the power circuitry.
Figure 4 illustrates the recommended grounding architecture.

A4490 Support

onents

Com

A4490

Local “Quiet’
Groun d Plane

Figure 4. Ground plane configurations

GND PGND

Thermal Vias

Internal Ground Plane

Power Circuitry

Cin

D

Star Connect ion

Cout

To avoid ground bounce and offset issues, it is highly recom­mended that the ground referenced feedback resistors (R2, R4,
and R6) should be connected as close to the GND connection of
the A4490 as possible.

A local quiet ground plane around these components can be
implemented, however, this ground plane should have a high
impedance connection to the star connection of the power stages.

If a ground plane is used, it is recommended that it does not
overlap the switching nodes (LX1, LX2, and LX3) to avoid the
possibility of noise pick-up. To minimize the possibility of noise
injection issues, it is recommended to isolate the ground plane
around high impedance nodes such as: FBx, ENBx and CPOR.

In terms of grounding the power components, a star connection
should be made to minimize the ground loop impedances. Note
that although a ground plane may be required to meet the thermal
characteristics of the solution it is still imperative to implement
a ground star connection for the power components. The ground
for the charge pump (PGND) should be connected to the thermal
vias.

Figures 5 and 6 below illustrates the importance of keeping the
ground connections as short as possible and forming good star
connections.

Figure 5 also illustrates the current conduction paths during the
on-cycle of the switching FET. The following points should be
noted:

• The capacitor C

should be placed as close as possible to the

IN

VBB terminals. The capacitance should be split between the VBB
terminals for V

REG1

and V

and the VBB terminal for V

REG3

REG2

.

Q

V

BB

C

IN

Figure 5. FET on-cycle current conduction paths

LX

D

Star Connection

L

V

REG

C

OUT

R

LOAD

V

BB

C

IN

Figure 6. FET off-cycle current conduction paths

Q

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115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

LX

Star Connection

L

V

REG

D

C

OUT

R

LOAD

14

A4490

V

V

V

T riple Output Step-Down Switching Regulator

The VBB terminals for V
via short and wide traces to the VBB terminal for V

REG1

and V

should be connected

REG2

REG3

.

• Each inductor should be connected as close as possible to the
respective switching FET (LX1, LX2, and LX3) and output
capacitors.

Figure 6 shows the current conduction path during the off-cycle
of the switching FET. The following points should be noted:

• The diode D should be placed as close as possible to both the
switching FET and the inductor.

6 to 34 V

Only VBB supplied

VBB

VDD

6 to 34 V

L

LX

D

REG

C

VDD applied externally (first option)

VBB

VDD

• Support components: POR capacitor (C11), charge pump ca-

pacitor (C1), reservoir capacitor (C2), and VDD filter capacitor

(C12) should be located as close as possible to their respective

terminal connections. The ground referenced capacitors should

be connected as close to the GND terminal as possible.

Powering Configurations The following three diagrams show

typical configurations for providing power to the application. The

middle diagram corresponds to the typical application shown on

the front page.

VDD applied externally (second option)

4.5 to 5.5 V

VDD

VBB

LX

L

LX

D

REG

C

L

REG

D

C

Comments:

- Simple configuration, only one supply required

- Increased power losses at higher VBB voltages

start-up = 4.3 V (typical), shutdown = 4.2 V

- V

BB

(typical)

Comments:

- Reduced power losses at higher VBB voltages
start-up = 4.3 V (typical), shutdown = 3.4 V

- V

BB

(typical). In this case, the start-up threshold
(V

BBUV(su)

) is lower because V

is not present

REG

Comments:

- Power restricted as V
of buck switches

R

DS(on)

start-up = 4.1 V (typical), shutdown = 3.4 V (typical)

- V

BB

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< 6 V, due to increase in

BB

15

A4490

21X

T riple Output Step-Down Switching Regulator

Package ES, 20-Pin QFN

0.30

4.00 ±0.15

20

1

A

2

4.00 ±0.15

D

C0.08

+0.05

0.25

–0.07

0.50

+0.15

0.40

–0.10

2
1

B

20

2.60

2.60

SEATING
PLANE

0.75 ±0.05

C

0.95

For Reference Only
(reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown

A

Terminal #1 mark area

B

Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)

C

Reference land pattern layout (reference IPC7351
QFN50P400X400X80-21BM)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

D

Coplanarity includes exposed thermal pad and terminals

20

1
2

C

PCB Layout Reference View

2.60

4.10

0.50

2.60

4.10

Copyright ©2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per­mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

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115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

16