Datasheet A3982 Datasheet (ALLEGRO)

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A3982

DMOS Stepper Motor Driver with Translator

OUT2A

SENSE2

VBB2

OUT2B

ENABLE

PGND

PGND

CP1

CP2

VCP

VREG

MS1

Package LB

1

2

3

4

5

6

7

Charge

Reg

Translator

Pump

8

9

10

11

12

Approximate Scale 1:1

The A3982 is a complete stepper motor driver with built-in translator
for easy operation. It is designed to operate bipolar stepper motors in
full- and half-step modes, with an output drive capacity of up to 35 V

OUT1A

24

SENSE1

23

VBB1

22

OUT1B

21

DIR

20

PGND

19

PGND

18

REF

OSC

17

16

15

14

13

STEP

VDD

ROSC

RESET

& Control Logic

and ±2 A. The A3982 includes a fixed off-time current regulator which
has the ability to operate in Slow or Mixed decay modes.

The translator is the key to the easy implementation of the A3982.
Simply inputting one pulse on the STEP input drives the motor one
step. There are no phase sequence tables, high frequency control lines,
or complex interfaces to program. The A3982 interface is an ideal fit
for applications where a complex microprocessor is unavailable or is
overburdened.

The chopping control in the A3982 automatically selects the current
decay mode (Slow or Mixed). When a signal occurs at the STEP input
pin, the A3982 determines if that step results in a higher or lower
current in each of the motor phases. If the change is to a higher current,
then the decay mode is set to Slow decay. If the change is to a lower
current, then the current decay is set to Mixed (set initially to a fast
decay for a period amounting to 31.25% of the fixed off-time, then
to a slow decay for the remainder of the off-time). This current decay
control scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.

Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.

AB SO LUTE MAX I MUM RAT INGS

Load Supply Voltage,V
Output Current, I

OUT

Logic Input Voltage, V
Sense Voltage, V

SENSE

Reference Voltage, V
Operating Temperature Range
Ambient, T

................................. –20°C to 85°C

A

Junction Temperature, T

Storage Temperature, T

*

Output current rating may be limited by duty cycle,

...................................35 V

BB

......................................... ±2 A

..................... –0.3 V to 7 V

IN

.......................................0.5 V

………..........................4 V

REF

.....................150°C

J(MAX)

.................... –55°C to 150°C

S

ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified current
rating or a junction temperature of 150°C.

26184.28B

Internal circuit protection includes: thermal shutdown with hysteresis,
undervoltage lockout (UVLO), and crossover-current protection.
Special power-on sequencing is not required.

*

The A3982 is supplied in a 24-pin wide-body SOIC (package LB) with

internally-fused power ground leads. It is also available in a lead (Pb)

free version (suffix –T), with 100% matte tin plated leadframes.

FEATURES

 Low R
 Automatic current decay mode detection/selection
 Mixed and Slow current decay modes
 Synchronous rectification for low power dissipation
 Internal UVLO and thermal shutdown circuitry
 Crossover-current protection

Use the following complete part number when ordering:

Part Number Pb-free Package Ambient

A3982SLB –

A3982SLB-T Yes

DS(ON)

outputs

24-pin, Wide SOIC –20°C to 85°C

DMOS Stepper Motor Driver with Translator

Functional Block Diagram

0.22 μF

A3982

0.1 μF

VDD

REF

STEP

DIR

RESET

MS1

ENABLE

DAC

Translator

VREG

Current

Regulator

PWM Latch

Blanking

Mixed Decay

Control

Logic

PWM Latch

Blanking

Mixed Decay

OSC

ROSC

Gate
Drive

DMOS Full Bridge

DMOS Full Bridge

CP1

Charge

Pump

CP2

VCP

VBB1

OUT1A

OUT1B

SENSE1

VBB2

OUT2A

OUT2B

SENSE2

0.1 μF

R

S1

R

S2

26184.28B

DAC

V

REF

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

2

A3982

DMOS Stepper Motor Driver with Translator

ELECTRICAL CHARACTERISTICS1 at T

Characteristics Symbol Test Conditions Min.

= 25°C, V

A

= 35 V (unless otherwise noted)

BB

Typ.

2

Max. Units

Output Drivers

Load Supply Voltage Range V
Logic Supply Voltage Range V

Output On Resistance R

Body Diode Forward Voltage V

Motor Supply Current I

Logic Supply Current I

BB

DD

DSON

F

BB

DD

Operating 8 – 35 V
Operating 3.0 – 5.5 V
Source Driver, I
Sink Driver, I

= –1.5 A – 0.370 0.460 Ω

OUT

= 1.5 A – 0.330 0.380 Ω

OUT

Source Diode, IF = –1.5 A – – 1.2 V
Sink Diode, I
f

< 50 kHz – – 4 mA

PWM

= 1.5 A – – 1.2 V

F

Operating, outputs disabled – – 2 mA
f

< 50 kHz – – 8 mA

PWM

Outputs off – – 5 mA

Control Logic

Logic Input Voltage

Logic Input Current

Input Hysteresis V

Blank Time

t

Fixed Off-Time

Reference Input Voltage Range V
Reference Input Current I

Current Trip-Level Error

3

Crossover Dead Time t

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

HYS(IN)

BLANK

t

OFF

REF

REF

err

I

DT

V

×0.7

DD

––

VIN = V

V

= V

IN

DD

DD

×0.7

×0.3

–20 <1.0 20 μA

–20 <1.0 20 μA

150 300 500 mV

0.7 1 1.3 μs

OSC > 3 V 20 30 40 μs
R

= 25 kΩ 23 30 37 μs

OSC

0–4V

–3 0 3 μA

V

REF

V

REF

= 2 V, %I
= 2 V, %I

= 70.71% – – ±5 %

TripMAX

= 100.00% – – ±5 %

TripMAX

100 475 800 ns

––V

V

×0.3

DD

V

Protection

Thermal Shutdown Temperature T
Thermal Shutdown Hysteresis T
UVLO Enable Threshold UV
UVLO Hysteresis UV

1

Negative current is defined as coming out of (sourcing from) the specified device pin.

2

Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for

individual units, within the specified maximum and minimum limits.

3

errI = (I

Trip – IProg

) ⁄ I

Prog

, where I

Prog

= %I

TripMAX

J

JHYS

LO

HYS

×

VDD rising 2.35 2.7 3 V

I

.

TripMAX

– 165 – °C
–15–°C

0.05 0.10 – V

26184.28B

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

3

A3982

DMOS Stepper Motor Driver with Translator

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

One-layer PCB, one-sided with copper limited to solder pads 77 ºC/W

One layer PCB, two-sided with copper limited to solder pads and

Package Thermal Resistance

R

θJA

3.57 in.

2

of copper area on each side, connected to PGND pins

High-K PCB (multilayer with significant copper areas, based on
JEDEC standard)

*In still air. Additional thermal information available on Allegro Web site.

Power Dissipation versus Ambient Temperature

4.00

45 ºC/W

35 ºC/W

3.50

3.00

(W)

D

2.50

2.00

1.50

Power Diss ipation, P

1.00

0.50

0

20 40 60 80 100 120 140 160

R

θJ

A

= 35 ºC/W

R

θJA

=45ºC/W

R

θJA

=77º

C/

W

Temperature, TA(°C)

26184.28B

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

4

A3982

DMOS Stepper Motor Driver with Translator

STEP

t

C

RESET, or DIR

MS1,

Time Duration Symbol Typ. Unit

STEP minimum, HIGH pulse width t

STEP minimum, LOW pulse width t

Setup time, input change to STEP t

Hold time, input change to STEP t

Figure 1. Logic Interface Timing Diagram

t

A

t

D

A

B

C

D

1 μs

1 μs

200 ns

200 ns

t

B

26184.28B

Table 1. Stepping Resolution Truth Table

MS1 Step Resolution Excitation Mode

L Full Step 2 Phase

H Half Step 1-2 Phase

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

5

A3982

DMOS Stepper Motor Driver with Translator

Functional Description

Functional Description

Device Operation. The A3982 is a complete stepper

motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full- and half-step modes. The currents in
each of the two output full-bridges and all of the N-channel
DMOS FETs are regulated with fixed off-time PMW (pulse
width modulated) control circuitry. At each step, the current
for each full-bridge is set by the value of its external current­sense resistor (R
the output voltage of its DAC (which in turn is controlled by
the output of the translator).

At power-on or reset, the translator sets the DACs and the
phase current polarity to the initial Home state (shown in
figures 2 and 3), and the current regulator to Mixed Decay
Mode for both phases. When a step command signal occurs
on the STEP input, the translator automatically sequences
the DACs to the next level and current polarity. (See table 2
for the current-level sequence.) The step resolution is set by
input MS1, as shown in table 1.

When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
for the active full-bridge is set to Mixed. If the new output
levels of the DACs are higher than or equal to their previous
levels, then the decay mode for the active full-bridge is set to
Slow. This automatic current decay selection improves step­ping performance by reducing the distortion of the current
waveform that results from the back EMF of the motor.

or RS2), a reference voltage (V

S1

REF

), and

increment is determined by input MS1, as shown in table 1.

Direction Input (DIR). This determines the direction of

rotation of the motor. When low, the direction will be clock­wise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.

Internal PWM Current Control. Each full-bridge is

controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, I
tially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and
the current sense resistor, RSx. When the voltage across R
equals the DAC output voltage, the current sense compara­tor resets the PWM latch. The latch then turns off either the
source DMOS FET (when in Slow Decay Mode) or the sink
and source DMOS FETs (when in Mixed Decay Mode).

The maximum value of current limiting is set by the selec­tion of R

and the voltage at the VREF pin. The transcon-

Sx

ductance function is approximated by the maximum value of
current limiting, I

TripMAX

I

(A), which is set by

TripMAX

= V

REF

/ ( 8 × RS)

where RS is the resistance of the sense resistor (Ω) and V
is the input voltage on the REF pin (V).

The DAC output reduces the V

output to the current

REF

sense comparator in precise steps, such that

TRIP

. Ini-

Sx

REF

RESET Input (RESET). The RESET input sets the

translator to a predefined Home state (shown in figures 2
and 3), and turns off all of the DMOS outputs. All STEP
inputs are ignored until the RESET input is set to high.

Step Input (STEP). A low-to-high transition on the STEP

input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of the

26184.28B

I

= (%I

trip

(See table 2 for %I

TripMAX

TripMAX

/ 100)

×

at each step.)

I

TripMAX

It is critical that the maximum rating (0.5 V) on the SENSE1
and SENSE2 pins is not exceeded.

Fixed Off-Time. The internal PWM current control cir-

cuitry uses a one-shot circuit to control the duration of time
that the DMOS FETs remain off. The one shot off-time, t

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

OFF

6

,

A3982

DMOS Stepper Motor Driver with Translator

is determined by the selection of an external resistor con­nected from the ROSC timing pin to ground. If the ROSC
pin is tied to an external voltage > 3 V, then t

defaults to

OFF

30 μs. The ROSC pin can be safely connected to the VDD
pin for this purpose. The value of t

t

≈ R

OFF

OSC

(μs) is approximately

OFF

⁄ 825

Blanking. This function blanks the output of the current

sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs
are blanked to prevent false overcurrent detection due to
reverse recovery currents of the clamp diodes, and switching
transients related to the capacitance of the load. The blank
time, t

(μs), is approximately

BLANK

t

BLANK

≈ 1 μs

Charge Pump (CP1 and CP2). The charge pump is

used to generate a gate supply greater than that of VBB
for driving the source-side DMOS gates. A 0.1 μF ceramic
capacitor, should be connected between CP1 and CP2. In
addition, a 0.1 μF ceramic capacitor is required between
VCP and VBB, to act as a reservoir for operating the
high-side DMOS gates.

VREG (VREG). This internally-generated voltage is

used to operate the sink-side DMOS outputs. The VREG
pin must be decoupled with a 0.22 μF ceramic capacitor to
ground. VREG is internally monitored. In the case of a fault
condition, the DMOS outputs of the A3982 are disabled.

Enable Input (ENABLE). This input turns on or off all

of the DMOS outputs. When set to a logic high, the outputs
are disabled. When set to a logic low, the internal control
enables the outputs as required. The translator inputs STEP,
DIR, and MS1, as well as the internal sequencing logic, all
remain active, independent of the ENABLE input state.

Shutdown. In the event of a fault, overtemperature

(excess TJ) or an undervoltage (on VCP), the DMOS out­puts of the A3982 are disabled until the fault condition is
removed. At power-on, the UVLO (undervoltage lockout)
circuit disables the DMOS outputs and resets the translator
to the Home state.

Mixed Decay Operation. The bridge can operate in

Mixed Decay Mode, depending on the step sequence, as
shown in figures 3 thru 5. As the trip point is reached, the
A3982 initially goes into a fast decay mode for 31.25%
of the off-time, t
Mode for the remainder of t

. After that, it switches to Slow Decay

OFF

OFF

.

Synchronous Rectification. When a PWM-off cycle

is triggered by an internal fixed–off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. This synchronous rectification feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS R
reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications.
Turning off synchronous rectification prevents the reversal of
the load current when a zero-current level is detected.

DSON

. This

26184.28B

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

7

A3982

DMOS Stepper Motor Driver with Translator

STEP

Phase 1

I

OUT1A

Direction = H

(%)

Phase 2

I

OUT2A

Direction = H

(%)

100.00

70.71

0.00

–70.71

–100.00

100.00

70.71

0.00

–70.71

–100.00

Home Microstep Position

Slow

Slow

Home Microstep Position

STEP

Phase 1

I

OUT1A

Direction = H

(%)

Phase 2

I

OUT2A

Direction = H

(%)

100.00

70.71

0.00

–70.71

–100.00

100.00

70.71

0.00

–70.71

–100.00

Slow

Slow

Mixed

Mixed

Home Microstep Position

Slow

Slow

Mixed

Mixed

Slow

Slow

Mixed

Home Microstep Position

Slow

Mixed

26184.28B

Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments

Table 2. Step Sequencing Settings

Home step position at Step Angle 45º; DIR = H

Half

Step

#

Phase 1

Current

[% I

tripMax

(%)

Full

Step

#

1 100.00 0.00 0.0

1 2 70.71 70.71 45.0

3 0.00 100.00 90.0

2 4 –70.71 70.71 135.0

5 –100.00 0.00 180.0

3 6 –70.71 –70.71 225.0

7 0.00 –100.00 270.0

4 8 70.71 –70.71 315.0

]

[% I

Phase 2

Current

tripMax

(%)

]

Step

Angle

(º)

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

8

DMOS Stepper Motor Driver with Translator

Pin List Table

Name Description Number

OUT2A DMOS Full Bridge 2 Output A 1

SENSE2 Sense resistor for Bridge 2 2

VBB2 Load supply 3

OUT2B DMOS Full Bridge 2 Output B 4

ENABLE Logic input 5

PGND Power ground 6

PGND Power ground 7

CP1 Charge pump capacitor 1 8

CP2 Charge pump capacitor 2 9

VCP Reservoir capacitor 10

VREG Regulator decoupling 11

MS1 Logic input 12

RESET Logic input 13

ROSC Timing set 14

VDD Logic supply 15

STEP Logic input 16

REF

PGND Power ground 18

PGND Power ground 19

DIR Logic input 20

1OUT1B DMOS Full Bridge 1 Output B 21

VBB1 Load supply 22

SENSE1 Sense resistor for Bridge 1 23

OUT1A DMOS Full Bridge 1 Output A 24

Current trip reference voltage input

A3982

17

26184.28B

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

9

DMOS Stepper Motor Driver with Translator

LB Package, 24-Pin Wide Body SOIC

A3982

Pins 6, 7, 18, and 19 are fused internally for enhanced thermal conductance.
Exact external appearance subject to vendor discretion, within the specifica­tions shown.

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required

to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned
to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for

its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

Copyright©2005 AllegroMicr osystems, Inc.

26184.28B

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

www.allegromicro.com

10