ALLEGRO A 3977 SLP-T Datasheet

A3977

Microstepping DMOS Driver with T ranslator

Features and Benefits

▪ ±2.5 A, 35 V output rating
▪ Low r

outputs, 0.45 Ω source, 0.36 Ω sink typical

DS(on)

▪ Automatic current decay mode detection/selection
▪ 3.0 to 5.5 V logic supply voltage range
▪ Mixed, fast, and slow current decay modes
▪ Home output
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection

Packages:

Package ED, 44-pin PLCC
with internally fused pins

Package LP, 28-pin TSSOP

with exposed thermal pad

Not to scale

Description

The A3977 is a complete microstepping motor driver, with built­in translator. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive
capability of 35 V and ±2.5 A. The A3977 includes a fixed
off-time current regulator that has the ability to operate in
slow-, fast-, or mixed-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.

The translator is the key to the easy implementation of the
A3977. Simply inputting one pulse on the STEP input drives the
motor one step (two logic inputs determine if it is a full-, half-,
quarter-, or eighth-step). There are no phase-sequence tables,
high-frequency control lines, or complex interfaces to program.
The A3977 interface is an ideal fit for applications where a
complex microprocessor is unavailable or over-burdened.

Internal synchronous-rectification control circuitry is provided
to improve power dissipation during PWM operation.

Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage lockout (UVLO) and crossover-current
protection. Special power-up sequencing is not required.

The A3977 is supplied in a choice of two power packages, a
44-pin plastic PLCC with 3 internally-fused pins on each of
four sides (suffix ED), and a thin (<1.2 mm), 28-pin TSSOP
with an exposed thermal pad (suffix LP). Both packages are
lead (Pb) free, with 100% matte tin leadframe plating.

26184.22J

Pin-out Diagram

GND

TRANSLATOR

& CONTROL LOGIC

232221

GND

1

LOAD

GND

SUPPLY

44 43 42

V

BB1

V

BB2

2

GND

LOAD

SUPPLY

REG

SLEEP

SR

ENABLE

41

RESET

40

2827262524

1A

OUT

65

NC

7

NC

8

PFD

9

1

RC

10

GND

11

12

GND

GND

13

REF

14

RC

2

15

LOGIC

SUPPLY

DD

V

16

NC NC

17 29

18

2A

OUT

1

HOME

DIR

SENSE

4321

PWM

TIMER

÷8

2019

221

MS

MS

SENSE

GND

GND

1B

OUT

39

38

37

36

CHARGE PUMP

35

34

33

32

31

30

2B

OUT

Dwg. PP-075-1

NC

CP

CP

V

GND

GND

GND

V

STEP

NC

2

1

CP

REG

A3977

Microstepping DMOS Driver with T ranslator

Selection Guide

Part Number Packing Package

A3977KEDTR-T 450 per reel 44-pin PLCC –40 to 125
A3977SEDTR-T 450 per reel 44-pin PLCC
A3977SLPTR-T 4000 per reel 28-pin TSSOP

Ambient Temperature, T

(°C)

–20 to 85

A

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage V

Logic Supply Voltage V

Logic Input Voltage Range V

Reference Voltage V

Sense Voltage (DC) V

Output Current I

Operating Ambient Temperature T

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature T

BB

DD

IN

REF

SENSE

OUT

A

stg

Pulsed, tw > 30 ns –0.3 to VDD+ 0.3 V

Pulsed, t

Output current rating may be limited by duty

cycle, ambient temperature, and heat sinking.

Under any set of conditions, do not exceed the

specified current rating or a junction temperature

of 150°C.

Range K –40 to 125 ºC

Range S –20 to 85 ºC

< 30 ns –1.0 to VDD+ 1 V

w

35 V

7.0 V

V

DD

0.5 V

±2.5 A

–55 to 150 ºC

V

Thermal Characteristics

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance

R

θJA

*Additional thermal information available on the Allegro website.

Package ED, on 4-layer PCB based on JEDEC standard 22 ºC/W

Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

2

A3977

U

C

Microstepping DMOS Driver with T ranslator

FUNCTIONAL BLOCK DIAGRAM

SUPPLY

SUPPLY

V

PFD

LOGIC

REF.

RC1

STEP

RESET

MS1
MS2

HOME

SLEEP

ENABLE

V

DD

REF

DIR

SR

UVLO

AND

LT

FA

4

TRANSLATOR

DA

2 V

+ -

PWM LATCH
BLANKING

MIXED DECAY

PWM TIMER

REGULATOR

BANDGAP

SENSE

CONTROL LOGIC

1

VREG

VCP

GATE DRIVE

CP2

CHARGE

PUMP

DMOS H BRIDGE

DMOS H BRIDGE

CP1

VCP

VBB1

OUT1A

OUT1B

SENSE1

VBB2

OUT2A

OUT2B

LOAD

SUPPLY

PFD

RC2

DAC

PWM TIMER

PWM LATCH
BLANKING
MIXED DECAY

+ -

SENSE2

Dwg. FP-050-2

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

3

A3977

Microstepping DMOS Driver with T ranslator

LP Pin-out

(TSSOP)

Table 1. Microstep Resolution Truth Table

MS1 MS2 Resolution

L L Full step (2 phase)
H L Half step
L H Quarter step
H H Eighth step

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

4

A3977

Microstepping DMOS Driver with T ranslator

ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers

Load Supply Voltage Range V

Output Leakage Current I

Output On Resistance r

DS(on)

Body Diode Forward Voltage V

Motor Supply Current I

DSS

Operating 8.0 – 35 V

BB

During sleep mode 0 – 35 V

V

= V

OUT

BB

V

= 0 V – <1.0 -20 μA

OUT

Source driver, I

Sink driver, I

= -2.5 A

OUT

= 2.5 A – 0.36 0.43 Ω

OUT

– <1.0 20 μA

– 0.45 0.57 Ω

Source diode, IF = -2.5 A – – 1.4 V

F

Sink diode, IF = 2.5 A – – 1.4 V

f

< 50 kHz – – 8.0 mA

PWM

Operating, outputs disabled

BB

– – 6.0 mA

Sleep mode – – 20 μA

Control Logic

Logic Supply Voltage Range V

Logic Input Voltage

Logic Input Current

Maximum STEP Frequency f

HOME Output Voltage

Blank Time t

Fixed Off Time t

Mixed Decay Trip Point

PFDH – 0.6V

PFDL – 0.21V

Ref. Input Voltage Range V

Reference Input Current I

Gain (Gm) Error (note 3) E

Crossover Dead Time t

V

V

I

IN(1)

I

IN(0)

STEP

V

V

BLANK

REF

REF

Operating 3.0 5.0 5.5 V

DD

IN(1)

IN(0)

VIN = 0.7V

VIN = 0.3V

DD

DD

0.7VDD ––V

– – 0.3V

-20 <1.0 20 μA

-20 <1.0 20 μA

500* – – kHz

IOH = -200 μA 0.7V

OH

IOL = 200 μA – – 0.3V

OL

DD

– – V

Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns

Rt = 56 kΩ, Ct = 680 pF 30 38 46 μs

off

DD

DD

Operating 0 – V

– 0 ±3.0 μA

V

= 2 V, Phase Current = 38.27% – – ±10 %

REF

V

G

DT

= 2 V, Phase Current = 70.71% – – ±5.0 %

REF

V

= 2 V, Phase Current = 100.00% – – ±5.0 %

REF

SR enabled 100 475 800 ns

DD

DD

–V

–V

DD

V

V

V

Continued on the next page…

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

5

A3977

Microstepping DMOS Driver with T ranslator

ELECTRICAL CHARACTERISTICS (continued) at T

= +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)

A

Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers (continued)

Thermal Shutdown Temp. T

Thermal Shutdown Hysteresis ∆T

UVLO Enable Threshold V

UVLO Hysteresis ∆V

Logic Supply Current I

* Operation at a step frequency greater than the specifi ed minimum value is possible but not warranteed.
NOTES:

1. Typical Data is for design information only.

2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.

3. EG = ([V

REF

/8] – V

SENSE

)/(V

REF

UVLO

/8)

J

J

UVLO

DD

Increasing V

f

PWM

Outputs off – – 10 mA

Sleep mode – – 20 μA

DD

< 50 kHz – – 12 mA

– 165 – °C

–15–°C

2.45 2.7 2.95 V

0.05 0.10 – V

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

6

A3977

Microstepping DMOS Driver with T ranslator

Functional Description

Device Operation. The A3977 is a complete microstep-

ping motor driver with built in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter- and eighth-step
modes. The current in each of the two output full-bridges,
all N-channel DMOS, is regulated with fi xed off-time
pulse-width modulated (PWM) control circuitry. The full­bridge current at each step is set by the value of an external
current sense resistor (R

), a reference voltage (V

S

REF

), and
the DACs output voltage controlled by the output of the
translator.

At power up, or reset, the translator sets the DACs
and phase current polarity to initial home state (see fi gures
for home-state conditions), and sets the current regula­tor for both phases to mixed-decay mode. When a step
command signal occurs on the STEP input the translator
automatically sequences the DACs to the next level (see
table 2 for the current level sequence and current polarity).
The microstep resolution is set by inputs MS

and MS2

1

as shown in table 1. If the new DAC output level is lower
than the previous level the decay mode for that full-bridge
will be set by the PFD input (fast, slow, or mixed decay).
If the new DAC level is higher or equal to the previous
level then the decay mode for that full-bridge will be slow
decay. This automatic current-decay selection will improve
microstepping performance by reducing the distortion of
the current waveform due to the motor BEMF.

Reset Input (RESET). The RESET input (active low)

sets the translator to a predefi ned home state (see fi gures
for home state conditions) and turns off all of the DMOS
outputs. The HOME output goes low and all STEP inputs
are ignored until the RESET input goes high.

Home Output (HOME). The HOME output is a logic

output indicator of the initial state of the translator. At
power up the translator is reset to the home state (see fi g-
ures for home state conditions).

Step Input (STEP). A low-to-high transition on the

STEP input sequences the translator and advances the
motor one increment. The translator controls the input to
the DACs and the direction of current fl ow in each wind-
ing. The size of the increment is determined by the state of
inputs MS

Microstep Select (MS

and MS2 (see table 1).

1

and MS2). Input terminals

1

MS1 and MS2 select the microstepping format per
table 1. Changes to these inputs do not take effect until the
STEP command (see fi gure).

Direction Input (DIR). The state of the DIRECTION

input will determine the direction of rotation of the motor.

Internal PWM Current Control. Each full-bridge is

controlled by a fi xed off-time PWM current-control cir-
cuit that limits the load current to a desired value (I

TRIP

).
Initially, a diagonal pair of source and sink DMOS outputs
are enabled and current fl ows through the motor winding
and RS. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense compara­tor resets the PWM latch, which turns off the source driver
(slow-decay mode) or the sink and source drivers (fast- or
mixed-decay modes).

The maximum value of current limiting is set by the

selection of R

and the voltage at the V

S

input with a

REF

transconductance function approximated by:

max = V

I

TRIP

The DAC output reduces the V

/8R

REF

S

output to the cur-

REF

rent-sense comparator in precise steps (see table 2 for %

I

max at each step).

TRIP

I

TRIP

= (% I

max/100) x I

TRIP

TRIP

max

It is critical to ensure that the maximum rating (0.5 V)
on the SENSE terminal is not exceeded. For full-step
mode, V
VDD, because the peak sense value is 0.707 x V
other modes V

can be applied up to the maximum rating of

REF

REF

should not exceed 4 V.

REF

/8. In all

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

7

A3977

Microstepping DMOS Driver with T ranslator

Functional Description (cont’d)

Fixed Off-Time. The internal PWM current-control

circuitry uses a one shot to control the time the drivers
remain off. The one shot off-time, t
the selection of an external resistor (R

, is determined by

off

) and capacitor (CT)

T

connected from the RC timing terminal to ground. The off­time, over a range of values of C

= 12 kΩ to 100 kΩ is approximated by:

R

T

t

= RTC

off

= 470 pF to 1500 pF and

T

T

RC Blanking. In addition to the fi xed off-time of the

PWM control circuit, the C

component sets the compara-

T

tor blanking time. This function blanks the output of the
current-sense comparator when the outputs are switched by
the internal current-control circuitry. The comparator out­put is blanked to prevent false over-current detection due
to reverse recovery currents of the clamp diodes, and/or
switching transients related to the capacitance of the load.
The blank time t

can be approximated by:

BLANK

t

= 1400C

BLANK

T

Charge Pump. (CP1 and CP2). The charge pump is

used to generate a gate supply greater than V

to drive

BB

the source-side DMOS gates. A 0.22 μF ceramic capacitor
should be connected between CP

and CP2 for pumping

1

purposes. A 0.22 μF ceramic capacitor is required between

and VBB to act as a reservoir to operate the high-side

V

CP

DMOS devices.

. This internally generated voltage is used to operate

V

REG

the sink-side DMOS outputs. The V
be decoupled with a 0.22 μF capacitor to ground. V

terminal should

REG

REG

is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.

Enable Input (ENABLE). This active-low input enables

all of the DMOS outputs. When logic high the outputs are
disabled. Inputs to the translator (STEP, DIRECTION,

, MS2) are all active independent of the ENABLE

MS

1

input state.

Shutdown. In the event of a fault (excessive junction

temperature, or low voltage on V

) the outputs of the

CP

device are disabled until the fault condition is removed. At
power up, and in the event of low V

, the undervoltage

DD

lockout (UVLO) circuit disables the drivers and resets the
translator to the HOME state.

Sleep Mode (SLEEP). An active-low control input used

to minimize power consumption when not in use. This
disables much of the internal circuitry including the output
DMOS, regulator, and charge pump. A logic high allows
normal operation and startup of the device in the home
position. When coming out of sleep mode, wait
1 ms before issuing a STEP command to allow the charge
pump (gate drive) to stabilize.

Percent Fast Decay Input (PFD). When a STEP input

signal commands a lower output current from the previous
step, it switches the output current decay to either slow-,
fast-, or mixed-decay depending on the voltage level at the
PFD input. If the voltage at the PFD input is greater than

0.6 V
on the PFD input is less than 0.21 V

then slow-decay mode is selected. If the voltage

DD

then fast-decay

DD

mode is selected. Mixed decay is between these two levels.
This terminal should be decoupled with a 0.1 μF capacitor.

Mixed Decay Operation. If the voltage on the PFD in-

put is between 0.6V

and 0.21VDD, the bridge will oper-

DD

ate in mixed-decay mode depending on the step sequence
(see fi gures). As the trip point is reached, the device will
go into fast-decay mode until the voltage on the RC termi­nal decays to the voltage applied to the PFD terminal. The
time that the device operates in fast decay is approximated
by:

= RTCTIn (0.6VDD/V

t

FD

After this fast decay portion, t

, the device will

FD

PFD

)

switch to slow-decay mode for the remainder of the fi xed
off-time period.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

8

A3977

Microstepping DMOS Driver with T ranslator

Functional Description (cont’d)

Synchronous Rectifi cation. When a PWM off-cycle is

triggered by an internal fi xed off-time cycle, load current
will recirculate according to the decay mode selected by
the control logic. The A3977 synchronous rectifi cation fea-
ture will turn on the appropriate MOSFETs during the cur­rent decay and effectively short out the body diodes with
the low r

driver. This will reduce power dissipation

DS(on)

signifi cantly and eliminate the need for external Schottky
diodes for most applications.

The synchronous rectifi cation can be set in either ac-

tive mode or disabled mode.

Timing Requirements

(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)

Active Mode. When the SR input is logic low, active

mode is enabled and synchronous rectifi cation will occur.

This mode prevents reversal of the load current by turning

off synchronous rectifi cation when a zero current level is

detected. This prevents the motor winding from conduct-

ing in the reverse direction.

Disabled Mode. When the SR input is logic high, syn-

chronous rectifi cation is disabled. This mode is typically

used when external diodes are required to transfer power

dissipation from the A3977 package to the external diodes.

A. Minimum Command Active Time

Before Step Pulse (Data Set-Up Time) ..... 200 ns

B. Minimum Command Active Time

After Step Pulse (Data Hold Time) ........... 200 ns

C. Minimum STEP Pulse Width ...................... 1.0 μs

D. Minimum STEP Low Time ......................... 1.0 μs

E. Maximum Wake-Up Time ......................... 1.0 ms

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

9

A3977

Microstepping DMOS Driver with T ranslator

Applications Information

Layout.

The printed wiring board should use a heavy ground

plane.

For optimum electrical and thermal performance, the

driver should be soldered directly onto the board.

The load supply terminal, V

, should be decoupled

BB

with an electrolytic capacitor (>47 μF is recommended)
placed as close to the device as possible.

To avoid problems due to capacitive coupling of the
high dv/dt switching transients, route the bridge-output
traces away from the sensitive logic-input traces. Always
drive the logic inputs with a low source impedance to in­crease noise immunity.

Grounding. A star ground system located close to the

driver is recommended.

The 44-lead PLCC has the analog ground and the
power ground internally bonded to the power tabs of the
package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35).

On the 28-lead TSSOP package, the analog ground
(lead 7) and the power ground (lead 21) must be con-

nected together externally. The copper ground plane located
under the exposed thermal pad is typically used as the star
ground.

Current Sensing. To minimize inaccuracies caused by

ground-trace IR drops in sensing the output current level,
the current-sense resistor (R

) should have an independent

S

ground return to the star ground of the device. This path
should be as short as possible. For low-value sense resis­tors the IR drops in the printed wiring board sense resistor’s
traces can be signifi cant and should be taken into account.
The use of sockets should be avoided as they can introduce
variation in R

Allegro MicroSystems recommends a value of R

due to their contact resistance.

S

S

given by

= 0.5/I

R

S

TRIP

max

Thermal Protection. Circuitry turns off all drivers when

the junction temperature reaches 165°C, typically. It is
intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has a
hysteresis of approximately 15°C.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

10

A3977

Microstepping DMOS Driver with T ranslator

Table 2. Step Sequencing

(DIR = L)

Phase 2 Phase 1
Full Half Quarter Eighth Current Current Step
Step # Step # Step # Step # [%I

max] [%I

trip

max] Angle

trip

1 1 1 0.00 100.00 0
2 19.51 98.08 11.25
2 3 38.27 92.39 22.50
4 55.56 83.15 33.75
1 2 3 5 70.71 70.71 45*
6 83.15 55.56 56.25
4 7 92.39 38.27 67.50
8 98.08 19.51 78.75
3 5 9 100.00 0.00 90
10 98.08 -19.51 101.25
6 11 92.39 -38.27 112.50
12 83.15 -55.56 123.75
2 4 7 13 70.71 -70.71 135
14 55.56 -83.15 146.25
8 15 38.27 -92.39 157.50
16 19.51 -98.08 168.75
5 9 17 0.00 -100.00 180
18 -19.51 -98.08 191.25
10 19 -38.27 -92.39 202.50
20 -55.56 -83.15 213.75
3 6 11 21 -70.71 -70.71 225
22 -83.15 -55.56 236.25
12 23 -92.39 -38.27 247.50
24 -98.08 -19.51 258.75
7 13 25 -100.00 0.00 270
26 -98.08 19.51 281.25
14 27 -92.39 38.27 292.50
28 -83.15 55.56 303.75
4 8 15 29 -70.71 70.71 315
30 -55.56 83.15 326.25
16 31 -38.27 92.39 337.50
32 -19.51 98.08 348.75

* Home state; HOME output low.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

11

A3977

Microstepping DMOS Driver with T ranslator

Full-Step Operation

MS1 = MS2 = L, DIR = H

The vector addition of the output currents at any step is
100%.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

12

A3977

Microstepping DMOS Driver with T ranslator

Half-Step Operation

MS1 = H, MS2 = L, DIR = H

The mixed-decay mode is controlled by the percent fast
decay voltage (V

). If the voltage at the PFD input is

PFD

greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between these
two levels.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

13

A3977

Microstepping DMOS Driver with T ranslator

Quarter-Step Operation

MS1 = L, MS2 = H, DIR = H

The mixed-decay mode is controlled by the percent fast
decay voltage (V

). If the voltage at the PFD input is

PFD

greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between these
two levels.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

14

A3977

Microstepping DMOS Driver with T ranslator

8 Microstep/Step Operation

MS1 = MS2 = H, DIR = H

The mixed-decay mode is controlled by the percent fast
decay voltage (V

). If the voltage at the PFD input is

PFD

greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between these
two levels.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

15

A3977

Terminal LP ED
Name Terminal Description (TSSOP) (PLCC)

GND Analog and power ground – 44, 1, 2
SENSE
HOME Logic output 2 4
DIR Logic Input 3 5
OUT1A DMOS H bridge 1 output A 4 6
NC No (internal) connection – 7, 8
PFD Mixed decay setting 5 9
RC1 Analog Input for fi xed offtime – bridge 1 6 10
GND Analog and power ground – 11, 12, 13
AGND Analog ground 7* –
REF Gm reference input 8 14
RC2 Analog input for fi xed offtime – bridge 2 9 15
LOGIC SUPPLY VDD, the logic supply voltage 10 16
NC No (internal) connection – 17
OUT2A DMOS H bridge 2 output A 11 18
MS2 Logic input 12 19
MS1 Logic input 13 20
SENSE2 Sense resistor for bridge 2 14 21
GND Analog and power ground – 22, 23, 24
LOAD SUPPLY2 VBB2, the load supply for bridge 2 15 25
SR Logic input 16 26
RESET Logic input 17 27
OUT2B DMOS H bridge 2 output B 18 28
NC No (internal) connection – 29, 30
STEP Logic input 19 31
VREG Regulator decoupling 20 32
PGND Power ground 21* –
GND Analog and power ground – 33, 34, 35
VCP Reservoir capacitor 22 36
CP1 Charge pump capacitor 23 37
CP2 Charge pump capacitor 24 38
NC No (internal) connection – 39
OUT1B DMOS H bridge 1 output B 25 40
ENABLE Logic input 26 41
SLEEP Logic input 27 42
LOAD SUPPLY1 VBB1, the load supply for bridge 1 28 43

Microstepping DMOS Driver with T ranslator

Terminal List

1 Sense resistor for bridge 1 1 3

* AGND and PGND on the TSSOP package must be connected together externally.

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

16

A3977

Microstepping DMOS Driver with T ranslator

ED Package, 44-pin PLCC

17.53 ±0.13

16.59 ±0.08
2144

0.51

17.53 ±0.13

44X

A

16.59 ±0.08

0.74 ±0.08

C0.10

0.43 ±0.10

7.75 ±0.367.75 ±0.36

For Reference Only
(reference JEDEC MS-018 AC)
Dimensions in millimeters
Internally fused pins 44, 1 and 2; 11-13; 22-24; and 33-35
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

A

Terminal #1 mark area

1.27

4.57 MAX

SEATING
PLANE

7.75 ±0.36

7.75 ±0.36

C

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

17

A3977

Microstepping DMOS Driver with T ranslator

LP Package, 28-pin TSSOP

28X

0.25

C0.10

+0.05
–0.06

9.70 ±0.10

28

B

4.40 ±0.10 6.40 ±0.20

3.00

A

21

5.00

0.65

SEATING
PLANE

1.20 MAX

0.10 MAX

C

For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

Terminal #1 mark area

A

Exposed thermal pad (bottom surface)

B
C

Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

4° ±4

+0.05

0.15

–0.06

0.60 ±0.15
(1.00)

0.25

SEATING PLANE

GAUGE PLANE

1.65

0.45

28

21

5.00

C

PCB Layout Reference View

0.65

3.00

6.10

Copyright ©2002-2010, Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per­mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

18