A3977
Microstepping DMOS Driver with T ranslator
Features and Benefits
▪ ±2.5 A, 35 V output rating
▪ Low r
outputs, 0.45 Ω source, 0.36 Ω sink typical
DS(on)
▪ Automatic current decay mode detection/selection
▪ 3.0 to 5.5 V logic supply voltage range
▪ Mixed, fast, and slow current decay modes
▪ Home output
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
Packages:
Package ED, 44-pin PLCC
with internally fused pins
Package LP, 28-pin TSSOP
with exposed thermal pad
Not to scale
Description
The A3977 is a complete microstepping motor driver, with builtin translator. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive
capability of 35 V and ±2.5 A. The A3977 includes a fixed
off-time current regulator that has the ability to operate in
slow-, fast-, or mixed-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3977. Simply inputting one pulse on the STEP input drives the
motor one step (two logic inputs determine if it is a full-, half-,
quarter-, or eighth-step). There are no phase-sequence tables,
high-frequency control lines, or complex interfaces to program.
The A3977 interface is an ideal fit for applications where a
complex microprocessor is unavailable or over-burdened.
Internal synchronous-rectification control circuitry is provided
to improve power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage lockout (UVLO) and crossover-current
protection. Special power-up sequencing is not required.
The A3977 is supplied in a choice of two power packages, a
44-pin plastic PLCC with 3 internally-fused pins on each of
four sides (suffix ED), and a thin (<1.2 mm), 28-pin TSSOP
with an exposed thermal pad (suffix LP). Both packages are
lead (Pb) free, with 100% matte tin leadframe plating.
26184.22J
Pin-out Diagram
GND
TRANSLATOR
& CONTROL LOGIC
232221
GND
1
LOAD
GND
SUPPLY
44 43 42
V
BB1
V
BB2
2
GND
LOAD
SUPPLY
REG
SLEEP
SR
ENABLE
41
RESET
40
2827262524
1A
OUT
65
NC
7
NC
8
PFD
9
1
RC
10
GND
11
12
GND
GND
13
REF
14
RC
2
15
LOGIC
SUPPLY
DD
V
16
NC NC
17 29
18
2A
OUT
1
HOME
DIR
SENSE
4321
PWM
TIMER
÷8
2019
221
MS
MS
SENSE
GND
GND
1B
OUT
39
38
37
36
CHARGE PUMP
35
34
33
32
31
30
2B
OUT
Dwg. PP-075-1
NC
CP
CP
V
GND
GND
GND
V
STEP
NC
2
1
CP
REG
A3977
Microstepping DMOS Driver with T ranslator
Selection Guide
Part Number Packing Package
A3977KEDTR-T 450 per reel 44-pin PLCC –40 to 125
A3977SEDTR-T 450 per reel 44-pin PLCC
A3977SLPTR-T 4000 per reel 28-pin TSSOP
Ambient Temperature, T
(°C)
–20 to 85
A
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage V
Logic Supply Voltage V
Logic Input Voltage Range V
Reference Voltage V
Sense Voltage (DC) V
Output Current I
Operating Ambient Temperature T
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature T
BB
DD
IN
REF
SENSE
OUT
A
stg
Pulsed, tw > 30 ns –0.3 to VDD+ 0.3 V
Pulsed, t
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150°C.
Range K –40 to 125 ºC
Range S –20 to 85 ºC
< 30 ns –1.0 to VDD+ 1 V
w
35 V
7.0 V
V
DD
0.5 V
±2.5 A
–55 to 150 ºC
V
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance
R
θJA
*Additional thermal information available on the Allegro website.
Package ED, on 4-layer PCB based on JEDEC standard 22 ºC/W
Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3977
U
C
Microstepping DMOS Driver with T ranslator
FUNCTIONAL BLOCK DIAGRAM
SUPPLY
SUPPLY
V
PFD
LOGIC
REF.
RC1
STEP
RESET
MS1
MS2
HOME
SLEEP
ENABLE
V
DD
REF
DIR
SR
UVLO
AND
LT
FA
4
TRANSLATOR
DA
2 V
+ -
PWM LATCH
BLANKING
MIXED DECAY
PWM TIMER
REGULATOR
BANDGAP
SENSE
CONTROL LOGIC
1
VREG
VCP
GATE DRIVE
CP2
CHARGE
PUMP
DMOS H BRIDGE
DMOS H BRIDGE
CP1
VCP
VBB1
OUT1A
OUT1B
SENSE1
VBB2
OUT2A
OUT2B
LOAD
SUPPLY
PFD
RC2
DAC
PWM TIMER
PWM LATCH
BLANKING
MIXED DECAY
+ -
SENSE2
Dwg. FP-050-2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3977
Microstepping DMOS Driver with T ranslator
LP Pin-out
(TSSOP)
Table 1. Microstep Resolution Truth Table
MS1 MS2 Resolution
L L Full step (2 phase)
H L Half step
L H Quarter step
H H Eighth step
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3977
Microstepping DMOS Driver with T ranslator
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range V
Output Leakage Current I
Output On Resistance r
DS(on)
Body Diode Forward Voltage V
Motor Supply Current I
DSS
Operating 8.0 – 35 V
BB
During sleep mode 0 – 35 V
V
= V
OUT
BB
V
= 0 V – <1.0 -20 μA
OUT
Source driver, I
Sink driver, I
= -2.5 A
OUT
= 2.5 A – 0.36 0.43 Ω
OUT
– <1.0 20 μA
– 0.45 0.57 Ω
Source diode, IF = -2.5 A – – 1.4 V
F
Sink diode, IF = 2.5 A – – 1.4 V
f
< 50 kHz – – 8.0 mA
PWM
Operating, outputs disabled
BB
– – 6.0 mA
Sleep mode – – 20 μA
Control Logic
Logic Supply Voltage Range V
Logic Input Voltage
Logic Input Current
Maximum STEP Frequency f
HOME Output Voltage
Blank Time t
Fixed Off Time t
Mixed Decay Trip Point
PFDH – 0.6V
PFDL – 0.21V
Ref. Input Voltage Range V
Reference Input Current I
Gain (Gm) Error (note 3) E
Crossover Dead Time t
V
V
I
IN(1)
I
IN(0)
STEP
V
V
BLANK
REF
REF
Operating 3.0 5.0 5.5 V
DD
IN(1)
IN(0)
VIN = 0.7V
VIN = 0.3V
DD
DD
0.7VDD ––V
– – 0.3V
-20 <1.0 20 μA
-20 <1.0 20 μA
500* – – kHz
IOH = -200 μA 0.7V
OH
IOL = 200 μA – – 0.3V
OL
DD
– – V
Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns
Rt = 56 kΩ, Ct = 680 pF 30 38 46 μs
off
DD
DD
Operating 0 – V
– 0 ±3.0 μA
V
= 2 V, Phase Current = 38.27% – – ±10 %
REF
V
G
DT
= 2 V, Phase Current = 70.71% – – ±5.0 %
REF
V
= 2 V, Phase Current = 100.00% – – ±5.0 %
REF
SR enabled 100 475 800 ns
DD
DD
–V
–V
DD
V
V
V
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3977
Microstepping DMOS Driver with T ranslator
ELECTRICAL CHARACTERISTICS (continued) at T
= +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)
A
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers (continued)
Thermal Shutdown Temp. T
Thermal Shutdown Hysteresis ∆T
UVLO Enable Threshold V
UVLO Hysteresis ∆V
Logic Supply Current I
* Operation at a step frequency greater than the specifi ed minimum value is possible but not warranteed.
NOTES:
1. Typical Data is for design information only.
2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.
3. EG = ([V
REF
/8] – V
SENSE
)/(V
REF
UVLO
/8)
J
J
UVLO
DD
Increasing V
f
PWM
Outputs off – – 10 mA
Sleep mode – – 20 μA
DD
< 50 kHz – – 12 mA
– 165 – °C
–15–°C
2.45 2.7 2.95 V
0.05 0.10 – V
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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