ALLEGRO A3965 User Manual
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These parts are in production but have been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications.
The device should not be purchased for new design applications
because obsolescence in the near future is probable. Samples are no
longer available.
A3965
DMOS Dual Full-Bridge PWM Motor Driver
Not for New Design
Date of status change: November 1, 2004
Recommended Substitutions:
The A3965 is a fairly unique device within Allegro’s portfolio, typically
fitting niche low-voltage, battery-driven stepper motor applications.
Our closest recommended alternatives are:
• For customers looking for a stepper motor driver for battery-driven
applications, we recommend the A3977, A3982, A3983, or A3984.
• The closest device functionally is the A3966, if supply current and a
low logic voltage (4.75 to 5.5 V) are not issues.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
PRELIMINARY DATASHEET - 12/4/2002
D
E
(Subject to change without notice)
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ..........................20 V
Output Current, I
Logic Supply Voltage, VDD..........................7.0 V
Logic Input Voltage Range,
VIN......................-0.3 V to V
(tW<30ns) ..................-1.0V to VDD +1V
Sense Voltage, V
Reference Voltage, V
Package Power Dissipation (TA = +25°C), P
A3965SLB........................... 50°C/W**
............................ ±500 mA*
OUT
DD
..................................0.5 V
SENSE
.................................3 V
REF
+ 0.3 V
D
3965
MOS DUAL FULL-BRIDG
PWM MOTOR DRIVER
Designed for Pulse Width Modulated (PWM) current control of low
voltage stepper motors, the A3965S is capable of output currents to ± 500 mA
and operating voltages to 20 V.
The A3965 is particularly attractive for low power or battery
operated motors where minimal power consumption is desired. A SLEEP
mode disables all circuitry and typically draws less than 1µA supply current
from motor and logic supply. During operation the fixed frequency ON
pulses of each H-bridge are 180 degrees out of phase to minimize the peak
demand required of the motor supply allowing savings in size and cost of
external power supply components.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a stepper motor with externally applied
PWM control signals.
Operating Temperature Range,
TA................................ -20°C to +85°C
Junction Temperature, TJ......................... +150°C
Storage Temperature Range,
TS............................... -55°C to +150°C
* Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
*Measured with 062" thick FR4, two sided PCB with 1 sq
inch copper area.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of V
current protection. Special power up sequencing is not required.
The A3965 is supplied in a 24-lead plastic SOIC with a copper
batwing tab (suffix ‘LB’).
and charge pump, and crossover
DD
FEATURES
±500 mA, 20 V Output Rating
2.85 to 5.5V Logic Supply Operation
Sleep Mode for Minimum Power Consumption
Fixed Frequency PWM
Offset On Pulses to Minimize Peak Supply Transient Currents
Internal UVLO and Thermal Shutdown Circuitry
Crossover-Current Protection
1
3965 DMOS Dual Full Bridge
PWM Motor Driver
Functional Block Diagram
V
SLEEP
PHASE2
PHASE1
ENABLE1
ENABLE2
.22uf
VREG
DD
UVLO AND
REGULATOR
FAULT
DETECT
BANDGAP
.22uf
CP2
CHARGE PUMP
CP1
V
CP
V
BB
.22uf
DMOS H-BRIDGE
V
CP
OUT
1A
OUT
1B
CONTROL
SENSE1
LOGIC
GATE
DRIVE
DMOS H-BRIDGE
V
BB
OUT
2A
OUT
2B
SENSE2
.1uF
RC
REF2
REF1
OSC
SENSE2
1/6
SENSE1
1/6
+-
SRQ
SRQ
+-
GROUND
2
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