ALLEGRO A3950 User Manual
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Preliminary Data Sheet
Subject to Change without Notice
November 4, 2005
Package LP, 16-pin TSSOP
with Exposed Thermal Pad
Control
Logic
Fault
Charge
Pump
NFAULT
MODE
PHASE
GND
SLEEP
ENABL
OUTA
SENSE
1
2
3
4
5
6
7
8
A3950
DMOS Full-Bridge Motor Driver
Designed for PWM (pulse width modulated) control of dc motors, the
A3950 is capable of peak output currents to ±2.8 A and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM
control signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
16
NC
15
VREG
14
VCP
13
GND
12
CP2
11
CP1
10
OUTB
9
VBB
Internal circuit protection includes motor lead short-to-supply / short-toground, thermal shutdown with hysteresis, undervoltage monitoring of
VBB and VCP, and crossover-current protection.
The A3950 is supplied in a thin profile (<1.2 mm overall height) 16-pin
TSSOP package with exposed thermal pad (package LP). It is lead (Pb)
free with 100% matte tin leadframe plating.
Approximate Scale 1:1
AB SO LUTE MAX I MUM RAT INGS
Load Supply Voltage, V
Output Current, I
Sense Voltage, V
BB.............................................
OUT.......................................................
.................................±500 mV
SENSE
VBB to OUTx.................................................... 36 V
OUTx to SENSE ................................................ 36 V
Logic Input Voltage, V
..........................–0.3 to 7 V
IN
Operating Temperature Range
Ambient, T
Junction Temperature, T
Storage Temperature, T
, Range S .................... –20°C to 85°C
A
............................ 150°C
J(MAX)
................. –40°C to 125°C
S
36 V
2.8 A
FEATURES
Low R
Overcurrent protection
Motor lead short-to-supply protection
Short-to-ground protection
Sleep function
Synchronous rectification
Diagnostic output
Internal UVLO
Crossover-current protection
Use the following complete part numbers when ordering:
Part Number Packing
A3950SLP-T 96 pieces / tube
A3950SLPTR-T 13-in. reel, 4000 pieces / reel
DS(on)
outputs
A3950DS
Preliminary Data Sheet
Subject to Change without Notice
November 4, 2005
DMOS Full-Bridge Motor Driver
Functional Block Diagram
0.1 µF
CP2
CP1
A3950
VREG
22 µF
25 V
MODE
PHASE
ENABLE
SLEEP
NFAULT
Charge
Pump
Low-Side
Gate Supply
Bias
Supply
Control Logic
UVLO
STB
STG
TSD Warning
GND GND
Pad
Motor Lead
Protection
VBB
OUTA
OUTB
SENSE
VCP
VBB
0.1 µF
OUTA
OUTB
SENSE
0.1 µF
Load Supply
R
SENSE
100 µF
Control Logic Table
PHASE ENABLE MODE SLEEP OUTA OUTB
1
Pin
Function
1 1 X 1 H L Forward
0 1 X 1 L H Reverse
X 0 1 1 L L Brake (slow decay)
1001LHFast Decay Synchronous Rectification
0001HLFast Decay Synchronous Rectification
XXX0ZZ
1X iindicates “don’t care,” Z indicates high impedence.
2To prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
A3950DS
Sleep Mode
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
2
2
Preliminary Data Sheet
Subject to Change without Notice
November 4, 2005
DMOS Full-Bridge Motor Driver
ELECTRICAL CHARACTERISTICS at TJ = 25°C, VBB = 8 to 36 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Units
f
< 50 kHz – 6 8.5 mA
Motor Supply Current I
PHASE, ENABLE, MODE Input
Voltage
SLEEP Input Voltage
PHASE, MODE Input Current
1
ENABLE Input Current
SLEEP Input Current
BB
V
V
V
V
I
I
I
I
I
I
NFAULT Output Voltage V
Input Hysteresis, except SLEEP V
Output On Resistance R
IHys
DS(on)
Propagation Delay Time t
Crossover Delay t
COD
Protection Circuitry
UVLO Threshold V
UVLO Hysteresis V
Overcurrent Threshold
2
Overcurrent Protection Period t
UVHys
I
OCP
OCP
Thermal Warning Temperature T
Thermal Warning Hysteresis T
Thermal Shutdown Temperature T
Thermal Shutdown Hysteresis T
1
For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2
Overcurrent protection is tested at 25°C in a restricted range and guaranteed by characterization.
JWHys
JTSD
JTSDHys
PWM
Charge pump on, outputs disabled – 3 4.5 mA
Sleep mode – – 10 μA
IH
IL
IH
IL
VIN = 2.0 V – <1.0 20 μA
IH
V
IL
IH
IL
IH
IL
OL
= 0.8 V – <–2.0 –20 μA
IN
VIN = 2.0 V – 40 100 μA
VIN = 0.8 V – 16 40 μA
VIN = 2.7 V – 27 50 μA
VIN = 0.8 V – <1 10 μA
I
= 1.0 mA – – 0.4 V
sink
2.0 – – V
– – 0.8 V
2.7 – – V
– – 0.8 V
100 150 200 mV
Source driver, I
Source driver, I
Sink driver, I
Sink driver, I
= -2.8 A, TJ=25°C – 0.35 0.48 Ω
OUT
= -2.8 A, TJ=125°C – 0.55 0.8 Ω
OUT
= 2.8 A, TJ=25°C – 0.3 0.43 Ω
OUT
= 2.8 A, TJ=125°C – 0.45 0.7 Ω
OUT
PWM, change to source or sink ON – 600 – ns
pd
PWM, change to source or sink OFF – 100 – ns
– 500 – ns
VBB increasing – 6.5 – V
UV
– 250 – mV
3––A
– 1.2 – ms
Temperature increasing – 160 – °C
JW
Recovery = TJW – T
JWHys
–15–°C
Temperature increasing – 175 – °C
Recovery = T
JTSD
– T
JTSDHys
–15–°C
A3950
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance R
*Additional thermal data available on the Allegro Web site.
A3950DS
4-layer PCB based on JEDEC standard 34 ºC/W
θJA
2-layer PCB with 3.8 in.
2
copper both sides, connected by thermal vias 43 ºC/W
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
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