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Package UA, 3-pin SIP
A3250 and A3251
Field-Programmable, Chopper-Stabilized
Unipolar Hall-Effect Switches
The A3250 and A3251 are field-programmable, chopper-stabilized, unipolar Halleffect switches designed for use in high-temperature applications. These devices
use a chopper-stabilization technique to eliminate offset inherent in single-element
devices.
The A3250 and A3251 are externally programmable devices. The devices have a
wide range of programmability of the magnetic operate point (B
teresis remains fixed. This advanced feature allows for optimization of the sensor
switchpoint and can drastically reduce the effects of variations found in a production environment, such as magnet and device placement tolerances.
These devices provide on-chip transient protection. A Zener clamp on the power
supply protects against overvoltage conditions on the supply line. These devices
also include short-circuit protection on the output.
) while the hys-
OP
TL Option
231
1. VCC
2. GND
3. VOUT
AB SO LUTE MAX I MUM RAT INGS
Supply Voltage, VCC ......................................26.5 V
Reverse-Supply Voltage, V
Zener Overvoltage, V
Output Current, I
Magnetic Flux Density, B.........................Unlimited
Operating Temperature
Ambient, T
Ambient, T
Maximum Junction, T
Storage Temperature, T
Z
.........................................20 mA
OUT
, Range J................. –40ºC to 115ºC
A
, Range L................–40ºC to 150ºC
A
........................–18 V
RCC
.......................................30 V
........................165ºC
J(max)
.................. –65ºC to 170ºC
S
The output of the A3250 switches LOW when subjected to a south-polarity magnetic field with a flux density that exceeds the threshold for B
HIGH when the field drops below the magnetic release point, B
, and switches
OP
. The output of
RP
the A3251 has the opposite polarity, switching HIGH in a south-polarity magnetic
field that B
, and switching LOW when the field drops below B
OP
RP
.
The other differences in the devices are the power-on state. The A3250 powers-on
in the HIGH state, while the A3251 powers-on in the LOW state.
These devices are available in a TO-92 three-lead ultra-mini SIP (Single In-line
Package), with either straight or formed and trimmed lead configuration.
Features and Benefits
Chopper stabilization for stable switchpoints
throughout operating temperature range
Externally programmable operate point
(through VCC pin)
On-board voltage regulator for 4.2 V to 24 V
operation
Use the following complete part numbers when ordering:
T
Part Number Package
A3250JUA
A3250JUATL
A3250LUA
A3250LUATL
A3251JUA
A3251JUATL
A3251LUA
A3251LUATL
*In south polarity magnetic field of sufficient strength.
Straight lead
Formed lead
Straight lead
Formed lead
Straight lead
Formed lead
Straight lead
Formed lead
A
(ºC)
–40 to 115 18
–40 to 150 13
–40 to 115 18
–40 to 150 13
On-chip protection against:
Supply transients
Output short-circuits
Reverse-battery condition
B
hys(typ)
(G)
Power-On Running*
V
OUT
High Low
Low High
A3250-DS
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3250 and A3251
B
OP
B
RP
B
HYS
Switch to High
Switch to Low
B+
V
OUT(off)
V
OUT
V
OUT(on)(sat)
V+
Hysteresis of ∆V
OUT
Switching Due to ∆B
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Functional Block Diagram
VCC
Program/Lock
Programming
Logic
Regulator
A3250
Hysteresis of ∆V
Switching Due to ∆B
V+
OUT
Switch to Low
Offset Adjust
Amp
Cancellation
Dynamic Offset
Low-Pass
Sample and Hold
Filter
Current Limit
GND
VOUT
Hysteresis Curves
A3251
V
OUT(off)
A3250-DS
OUT
V
Switch to High
RP
B
B
HYS
V
OUT(on)(sat)
B
OP
B+
Output voltage in relation to sensed magnetic flux density in a
south polarity magnetic field of sufficient strength. Transition
through B
must precede transition through BRP.
OP
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
OPERATING CHARACTERISTICS valid over operating TA and VCC, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage
1
Output Saturation Voltage V
Output Leakage Current I
Supply Current
Output Rise Time t
Output Fall Time t
Chopping Frequency f
Power-Up Time t
Output Current Limit
1,2
Power-On State POS
MAGNETIC CHARACTERISTICS
V
CC
OUT(sat)IOUT
OFF
Running mode 4.2 – 24 V
V
A3250; B < BRP; V
I
CC(off)
A3251; B > B
A3250; B > BOP; V
I
CC(on)
r
f
C
on
I
OUT(lim)
A3251; B < B
R
R
V
Short-circuit protection 60 90 120 mA
A3250; B < B
A3251; B < B
= 20 mA; Switch state = ON – 175 400 mV
= 24 V; Switch state = OFF – – 10 µA
OUT
= HIGH – 4.0 7.0 mA
OUT
; V
OP
RP
= 820 Ω, C
LOAD
= 820 Ω, C
LOAD
= HIGH – 20 50 µs
OUT
RP
RP
= HIGH – 4.0 7.0 mA
OUT
= LOW – 6.0 10.0 mA
OUT
; V
= LOW – 6.0 10.0 mA
OUT
= 10 pF – – 5.0 µs
LOAD
= 10 pF – – 5.0 µs
LOAD
, t > t
on
, t > t
on
– 340 – kHz
– HIGH – mV
– LOW – mV
Initial Operate Point B
Temperature Drift of B
OP
∆B
OP
BOP ≤ 500 gauss –35 – 35 G
OP
–20 13 50 G
Package TA range = J 5.0 18 35 G
Hysteresis (B
– BRP)B
OP
hys
Package T
range = L 5.0 13 35 G
A
PROGRAMMING CHARACTERISTICS
Programmable B
OP
Values
3
B
OP(prog)
50 – ≥350 G
Switchpoint set – 6 – Bit
Number of Programming Bits –
Programming lock – 1 – Bit
Resolution B
RES
– 7.0 – G
TRANSIENT PROTECTION CHARACTERISTICS
Supply Zener Voltage V
Supply Zener Current I
Reverse Battery Current I
1
Do not exceed TJ(max): Additional information on power derating is provided in the applications section.
2
Short-circuit protection is not intended for continuous operation; permanent damage may result.
3
Device can be used below 50 G but is not guaranteed to be a unipolar switch. It is the responsibility of the programmer to verify that the desired
switchpoint has been achieved.
Z
Z
RCC
VCC = 28 V – – 13 mA
V
= –18 V, TJ < T
RCC
J(max)
28 – – V
– – –5.0 mA
A3250-DS
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Typical Characterization Data
All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot
Average BOPvs. T
A
Program Code: 1, VCC=12V
30
25
(G)Average B
20
OP
15
10
5
Average B
0
-5
-50 -20 10 40 70 100 130 160
T
(°C)
A
Average BOPvs. T
A
Program Code: 8, VCC=12V
75
70
(G)Average B
65
OP
60
55
50
45
40
-50 -20 10 40 70 100 130 160
(°C)
T
A
Average BRPvs. T
A
Program Code: 1, VCC=12V
10
5
(G)Average B
0
RP
-5
-10
Average B
-15
-20
-50 -20 10 40 70 100 130 160
TA(°C)
Average BRPvs. T
A
Program Code: 8, VCC=12V
60
50
(G)Average B
RP
40
30
20
-50 -20 10 40 70 100 130 160
T
(°C)
A
130
125
(G)
120
OP
115
110
105
100
A3250-DS
Average BOPvs. T
A
Program Code: 16, VCC=12V
-50 -20 10 40 70 100 130 160
T
(°C)
A
Average BRPvs. T
A
Program Code: 16, VCC=12V
110
105
(G)
100
RP
95
90
85
80
-50 -20 10 40 70 100 130 160
(°C)
T
A
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A3250 and A3251
-40°C to 25°C and 150°C to 25°C
-30
-20
-10
0
10
20
30
Code 1
Code 8
Code 16
-40°C to 25°C
150°C to 25°C
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Typical Characterization Data
All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot
Average B
Program Code: 1, V
vs. Temperature
hys
CC
=12V
35
30
(G)
25
HYS
20
15
10
Average B
5
0
-50 -20 10 40 70 100 130 160
T
(°C)
A
Average B
Program Code: 8, V
vs. Temperature
hys
CC
=12V
35
30
(G)
25
HYS
20
15
10
Average B
5
0
-50 -20 10 40 70 100 130 160
(°C)
T
A
Average B
Program Code: 16, V
vs. Temperature
hys
CC
=12V
35
30
(G)
25
HYS
20
15
10
Average B
5
0
-50 -20 10 40 70 100 130 160
TA(°C)
Average BOPvs. Temperature
(G)
OP
Average B
(°C)
T
A
A3250-DS
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A3250 and A3251
(
)
(
)
(
)
(
)
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Typical Characterization Data
All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot
Average I
vs. Temperature
CC(on)
10
8
6
mA
on
4
CC
I
2
I
CC(on)
I
CC(on)
I
CC(on)
@3.8V
@12.0V
@26.5V
0
-50 -20 10 40 70 100 130 160
T
(°C)
A
Average V
V
CC
280
260
240
(mV)
220
200
OUT(SAT)
180
V
160
140
-50 -20 10 40 70 100 130 160
OUT(SAT)
= 3.8 V, I
T
10
8
6
mA
off
4
CC
I
2
0
-50 -20 10 40 70 100 130 160
vs. Temperature
=20mA
out
(°C)
A
Average I
vs. Temperature
CC(off)
TA(°C)
I
CC(off)
I
CC(off)
I
CC(off)
@3.8V
@12.0V
@26.5V
A3250-DS
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions Min. Typ. Max Units
Package Thermal Resistance
R
θJA
25
24
23
22
21
(V)
20
CC
19
18
17
16
15
14
13
12
11
10
9
Maximum Allowable V
8
7
6
5
4
3
2
20 40 60 80 100 120 140 160 180
Package UA, minimum-K PCB (single-sided with
copper limited to solder pads)
Power Derating Curve
T
= 165ºC; ICC=I
J(max)
Minimum-K PCB, Package UA
(R
= 165 ºC/W)
θJA
CC(max)
V
V
165 – – ºC/W
CC(max)
CC(min)
A3250-DS
Maximum Power Dissipation, P
1900
J(max)
CC(max);ICC=ICC(max)
T
= 165ºC; VCC=V
1800
1700
1600
1500
1400
1300
1200
(mW)
1100
D
Power Dissipation, P
1000
900
800
700
600
500
400
300
Minimum-K P
(R
θ
JA
=165
CB, Pac
º
C
/W)
kag
eUA
200
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)
D(max)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Chopper-Stabilized Technique
A3250 and A3251
Functional Description
The Hall sensor is based on a Hall element, a small sheet of
semiconductor material in which a constant bias current flows
when a constant voltage source is applied. The output takes the
form of a voltage measured across the width of the Hall element,
and has negligible value in the absence of a magnetic field.
When a magnetic field is applied with flux lines at right angles
to the current in the Hall element, a small signal voltage directly
proportional to the strength of the magnetic field occurs at the
output of the Hall element.
This small signal voltage is disproportionally small relative to
the offset produced at the input of the device. This makes it very
difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Therefore, it is important to reduce any distortion of the signal that
could be amplified when the signal is processed.
Chopper stabilization is a unique approach used to minimize
input offset on the Hall IC. This technique removes a key
source of output drift due to temperature and mechanical stress,
and produces a 3X reduction in offset in comparison to other,
conventional methods.
This offset reduction chopping technique is based on a signal modulation-demodulation process. The undesired offset
signal is separated from the magnetically-induced signal in the
frequency domain. The offset (and any low-frequency noise)
component of the signal can be seen as signal distortion added
after the signal modulation process has taken place. Therefore,
the dc offset is not modulated and remains a low-frequency
component. Consequently, the signal demodulation process acts
as a modulation process for the offset, causing the magneticallyinduced signal to recover its original spectrum at baseband while
the dc offset becomes a high-frequency signal. Then, the signal
passes using a low-pass filter, while the modulated dc offset is
suppressed.
The advantage of this approach is significant offset reduction,
which desensitizes the Hall IC against the effects of temperature
and mechanical stress. The disadvantage is that this technique
features a demodulator that uses a sample-and-hold block to
store and recover the signal. This sampling process can slightly
degrade the SNR (signal-to-noise ratio) by producing replicas of
the noise spectrum at the baseband. This degradation is a function
of the ratio between the white noise spectrum and the sampling
frequency. The effect of the degradation of the SNR is higher
jitter, also known as signal repeatability. However, the jitter in a
continuous-time device can be 5X that of the A3250/A3251.
A3250-DS
Regulator
Amp
Hold / LPF
Sample and
Chopper stabilization circuit (dynamic quadrature offset cancellation)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Programming Protocol
The operate switchpoint, B
, can be field-programmed. To do
OP
so, a coded series of voltage pulses through the VCC pin is used
to set bitfields in onboard registers. The effect on the device
output can be monitored, and the registers can be cleared and
set repeatedly until the required BOP is achieved. To make the
setting permanent, bitfield-level solid state fuses are blown, and
finally, a device-level fuse is blown, blocking any further coding. It is not necessary to program the release switchpoint, BRP ,
because the difference between BOP and BRP , referred to as the
hysteresis, B
The range of values between B
HYS
, is fixed.
OP(min)
and B
OP(max)
is scaled to
64 increments. The actual change in magnetic flux (G) represented by each increment is indicated by B
(see the Operating
RES
Characteristics table; however, testing is the only method for
verifying the resulting B
). For programming, the 64 incre-
OP
ments are individually identified using 6 data bits, which are
physically represented by 6 bitfields in the onboard registers.
By setting these bitfields, the corresponding calibration value is
programmed into the device.
Three voltage levels are used in programming the device: a low
voltage, V
, a minimum required to sustain register settings; a
PL
mid-level voltage, VPM , used to increment the address counter
in the device; and a high voltage, VPH , used to separate sets of
VPM pulses (when short in duration) and to blow fuses (when
long in duration). A fourth voltage level, essentially 0 V, is used
to clear the registers between pulse sequences. The pulse values
are shown in the Programming Protocol Characteristics table and
in figure 1.
V+
V
PH
V
PM
V
PL
T
0
T
d(1)
Figure 1. Pulse amplitudes and durations
d(P)
T
d(0)
t
Additional information on device programming and programming products is available on www. allegromicro.com. Programming hardware is available for purchase, and programming
software is available free of charge.
Code Programming. Each bitfield must be individually set. To
do so, a pulse sequence must be transmitted for each bitfield that
is being set to 1. If more than one bitfield is being set to 1, all
pulse sequences must be sent, one after the other, without allowing VCC to fall to zero (which clears the registers).
The same pulse sequence is used to provisionally set bitfields as
is used to permanently set bitfield-level fuses. The only difference is that when provisionally setting bitfields, no fuse-blowing
pulse is sent at the end of the pulse sequence.
PROGRAMMING PROTOCOL CHARACTERISTICS, TA = 25ºC, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
V
Programming Voltage
1
V
V
Programming Current
2
t
Pulse Width
t
t
Pulse Rise Time t
Pulse Fall Time t
1
Programming voltages are measured at the VCC pin.
2
A bypass capacitor with a minimum capacitance of 0.1 µF must be connected from VCC to the GND pin of the device in order to provide
Minimum voltage range during programming 4.5 5.0 5.5 V
PL
PM
PH
I
Maximum supply current during programming – 500 – mA
PP
OFF time between programming bits 20 – – µs
d(0)
Pulse duration (ON time) for enable, address, fuse
d(1)
blowing or lock bits
Pulse duration (ON time) for fuse blowing 100 300 – µs
d(P)
VPL to VPM; VPL to V
r
VPM to VPL; VPH to V
f
PH
PL
10 11 12 V
23 25 26 V
20 – – µs
11 – – µ s
5––µs
the current necessary to blow the fuse.
Allegro MicroSystems, Inc.
A3250-DS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A bitfield address sequence.
3. When permanently setting the bitfield, a long V
fuse-blow-
PH
ing pulse. (Note: Blown bit fuses cannot be reset.) When
provisionally trying a value, a short VPH pulse.
4. When permanently setting the bitfield, the level of V
CC
must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally setting bitfields, VCC must be maintained at VPL between pulse
sequences, in order to maintain the prior bitfield settings while
preparing to set additional bitfields.
Bitfields that are not set are evaluated as zeros. The bitfield-level
V+
V
PH
V
PM
V
PL
0
Figure 2. Pulse sequence to provisionally try calibration value 5 (101 binary, or bitfield
address 3 and bitfield address 1).
7 pulses
Enable
Address
Try 001002 (410)
fuses for 0 value bitfields are never blown. This prevents inadvertently setting the bitfield to 1. Instead, blowing the devicelevel fuse protects the 0 bitfields from being accidentally set in
the future.
Two pulse sequences for provisionally trying the calibration
value 5 are shown in figure 2. Because the bitfields must be set
individually, 510 must be programmed as binary 101. Bit 3 is
set to 1 (0001002, which is 410), then bit 1 is set to 1 (0000012,
which is 110). Bit 2 is ignored, and so remains 0.
Two pulse sequences for permanently setting the calibration
value 5 are shown in figure 3. The final VPH pulse, which was
used as a short delimiter when trying values, is maintained for a
longer period, enough to blow the corresponding bitfield-level
fuse.
Optional
Monitoring
7 pulses
Try 00001
(110)
2
Address
Optional
Monitoring
ClearEnable
t
A3250-DS
V+
V
PH
V
PM
V
PL
0
7 pulses
Enable
Address
Encode 001002 (410)
Blow BlowEnable
7 pulses
Encode 00001
Figure 3. Pulse sequence to permanently encode calibration value 5 (101 binary, or
bitfield address 3 and bitfield address 1).
Address
(110)
2
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
10
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Enabling Addressing Mode. The first segment of code is a
keying sequence used to enable the bitfield addressing mode. As
shown in figure 4, this segment consists of one short VPH pulse,
seven or more VPM pulses, and one VPH pulse, with no supply
interruptions. This sequence is designed to prevent the device
from being programmed accidentally, such as by noise on the
supply line.
Address Selection. After addressing mode is enabled, the
target bitfield address, is indicated by a series of VPM pulses,
as shown in figure 3. When provisionally trying a value, this
sequence is followed by a short VPH pulse, which serves to
delimit the address and set the corresponding bitfield. When
permanently setting a bitfield, the VPH pulse is continued for a
longer period of time, suffienct to not only set the bitfield to 1,
but also to blow the bitfield fuse.
V+
V
PH
V
PM
V
PL
0
Minimum 7 pulses
Figure 4. Addressing mode enable pulse sequence
V+
V
PH
V
PM
V
PL
0
Address 1
Address 2
Address n ( ≤ 63)
t
Lock Bit Programming. After the desired B
calibration value
OP
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 65) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 6.
A3250-DS
Figure 5. Pulse sequence to select addresses
V+
V
PH
V
PM
V
PL
0
Falling edge of final BOP address digit
7 pulses 65 pulses
Enable
Address Blow
Encode Lock Bit
Figure 6. Pulse sequence to encode lock bit
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
t
t
11
A3250 and A3251
GND
A3250/A3251
VCC
V
Supply
0.1 µF
A
R
L
C
BYP
R
S
100 Ω
1.2 kΩ
5V
VOUT
A
A
Maximum separation 5 mm
from C
BYP
to device
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Application Information
For additional general application information, visit the Allegro
MicroSystems Web site at www. allegromicro.com.
Typical Application Circuit
It is strongly recommended that an external ceramic bypass
capacitor, C
between the VCC pin and the supply and GND pin to reduce
both external noise and noise generated by the chopper-stabilization technique. (The diagram at the right shows C
C
should be installed so that the traces that connect it to the
BYP
A3250/A3251 are no greater than 5 mm in length.
, in the range of 0.01 µF to 0.1 µF be connected
BYP
at 0.1 µF.)
BYP
The series resistor RS, in combination with C
creates a filter
BYP
for EMI pulses. (Additional information on EMC is provided
on the Allegro MicroSystems Web site.) RS will have a drop
of approximately 800 mV. This must be taken into consideration when determining the minimum VCC requirement for the
A3250/A3251. The pull-up resistor, RL, should be chosen to
limit the current through the output transistor; do not exceed the
maximum continuous output current of the device.
Typical application circuit
A3250-DS
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
12
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Power Derating
The device must be operated below the maximum junction
temperature of the device, T
peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
relatively small component of R
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
P
= VIN × I
D
∆T = PD × R
. Under certain combinations of
J(max)
, is a figure of merit sum-
θJA
. Ambient air temperature,
θJA
IN
(2)
θJA
(1)
θJC
, is
Example: Reliability for VCC at TA = 150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
R
165°C/W, T
θJA =
I
CC(max) = 10
mA.
Calculate the maximum allowable power level, P
J(max) =
165°C, V
CC(max) =
24 V, and
D(max)
. First,
invert equation 3:
∆T
max
= T
– TA = 165 °C – 150 °C = 15 °C
J(max)
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= ∆T
max
÷ R
= 15°C ÷ 165 °C/W = 91 mW
θJA
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
÷ I
= 91 mW ÷ 10 mA = 9 V
CC(max)
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤V
Compare V
able operation between V
R
. If V
θJA
V
is reliable under these conditions.
CC(max)
CC(est)
CC(est)
to V
≥ V
. If V
CC(max)
CC(est)
CC(max)
CC(est)
and V
CC(max)
, then operation between V
≤ V
CC(max)
requires enhanced
.
CC(est)
, then reli-
CC(est)
and
T
= TA + ∆T (3)
J
For example, given common conditions such as: TA= 25°C,
V
= 12 V, I
CC
PD = VCC × I
∆T = PD × R
= 4 mA, and R
CC
= 12 V × 4 mA = 48 mW
CC
= 48 mW × 165 °C/W = 8°C
θJA
θJA
= 165 °C/W, then:
TJ = TA + ∆T = 25°C + 8°C = 33°C
A worst-case estimate, P
able power level (V
at a selected R
A3250-DS
θJA
CC(max)
and TA.
, represents the maximum allow-
D(max)
, I
), without exceeding T
CC(max)
J(max)
,
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
13
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
Package UA, 3-Pin; (TO-92)
A3250-DS
The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920;
5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038;
5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its
products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or sys tems without
express written approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc.
assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may
result from its use.
Copyright © 2004 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
14
A3250 and A3251
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
A3250-DS
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
15
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