ALLEGRO 3977 DATA SHEET

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3977

MICROSTEPPING DMOS DRIVER

WITH TRANSLATOR

Data Sheet

26184.22D

A3977xED

(PLCC)

1A

OUT

65

NC

7

NC

8

PFD

9

RC

10

1

GND

11

GND

12

GND

13

REF

14

RC

2

15

LOGIC

16

V

SUPPLY

DD

NC NC

17 29

18

2A

OUT

1

HOME

DIR

SENSE

4321

PWM

TIMER

÷8

2019

221

MS

MS

SENSE

GND

GND

ABSOLUTE MAXIMUM RATINGS

at TA = +25°C

Load Supply Voltage, VBB............. 35 V

Output Current, I

Logic Supply Voltage, VDD........... 7.0 V

Logic Input Voltage Range, V

(tw >30 ns)..... -0.3 V to VDD + 0.3 V

(tw <30 ns)........... -1 V to VDD + 1 V

Sense Voltage, V
Reference Voltage, V
Package Power Dissipation,

PD................................. See page 3

Operating Temperature Range, T

(A3977Kx) ............ -40°C to +125°C

(A3977Sx) .............. -20°C to +85°C

Junction Temperature, TJ......... +150°C

Storage Temperature Range,

TS......................... -55°C to +150°C

* Output current rating may be limited by
duty cycle, ambient temperature, and heat
sinking. Under any set of conditions, do not
exceed the specified current rating or a
junction temperature of 150°C.

OUT

SENSE

1

LOAD

GND

GND

SUPPLY

44 43 424140

V

BB1

TRANSLATOR

& CONTROL LOGIC

V

BB2

232221

2

GND

GND

LOAD

SUPPLY

REG

SLEEP

SR

ENABLE

RESET

1B

OUT

CHARGE PUMP

2827262524

2B

OUT

Dwg. PP-075-1

39

38

37

36

35

34

33

32

31

30

.................. ±2.5 A

IN

................. 0.5 V

................ V

REF

A

DD

NC

CP

CP

V

GND

GND

GND

V

STEP

NC

The A3977xED and A3977xLP are complete microstepping motor drivers
with built-in translator. They are designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive capability of 35
V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has
the ability to operate in slow-, fast-, or mixed-decay modes. This current­decay control scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.

2

1

CP

The translator is the key to the easy implementation of the A3977. By
simply inputting one pulse on the STEP input the motor will take one step
(full, half, quarter, or eighth depending on two logic inputs). There are no
phase-sequence tables, high-frequency control lines, or complex interfaces to
program. The A3977 interface is an ideal fit for applications where a complex

REG

µP is unavailable or over-burdened.

Internal synchronous-rectification control circuitry is provided to improve
power dissipation during PWM operation.

Internal circuit protection includes thermal shutdown with hysteresis,
under-voltage lockout (UVLO) and crossover-current protection. Special
power-up sequencing is not required.

The A3977 is supplied in a choice of two power packages, a 44-pin
plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28­pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is

available in a lead-free version (100% matte tin leadframe).

FEATURES

*

■ ±2.5 A, 35 V Output Rating

■ Low r

Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical

DS(on)

■ Automatic Current Decay Mode Detection/Selection

■ 3.0 V to 5.5 V Logic Supply Voltage Range

■ Mixed, Fast, and Slow Current Decay Modes

■ Home Output

■ Synchronous Rectification for Low Power Dissipation

■ Internal UVLO and Thermal Shutdown Circuitry

■ Crossover-Current Protection

Always order by complete part number:

Part Number Package

A3977KED 44-pin PLCC

A3977KLP 28-pin TSSOP

A3977SED 44-pin PLCC

A3977SED-T 44-pin PLCC; Lead-free

A3977SLP 28-pin TSSOP

A3977SLP-T 28-pin TSSOP; Lead-free

3977

MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

FUNCTIONAL BLOCK DIAGRAM

LOGIC

SUPPLY

REF.

SUPPLY

V

REF

RC

DD

1

UVLO

AND

FA

LT

DA

2 V

PWM LATCH
BLANKING
MIXED DECAY

REGULATOR

BANDGAP

SENSE

+-

CP

V

REG

2

CHARGE

CP

1

V

CP

LOAD

SUPPLY

PUMP

BB1

V

1

V

CP

DMOS H BRIDGE

OUT
OUT

1A

1B

V

PFD

STEP

DIR

RESET

MS
MS

HOME

SLEEP

SR

ENABLE

1
2

PFD

RC

4

TRANSLATOR

PWM TIMER

DMOS H BRIDGE

SENSE

V

BB2

1

GATE DRIVE

OUT

OUT

2A

2B

CONTROL LOGIC

PWM TIMER

PWM LATCH
BLANKING
MIXED DECAY

2

DAC

+-

SENSE

2

Dwg. FP-050-2

2

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 2002, 2003 Allegro MicroSystems, Inc.

A3977xLP

(TSSOP)

3977

MICROSTEPPING DMOS DRIVER

WITH TRANSLATOR

5.0

SENSE

SUPPLY

SENSE

1

1

HOME

2

3

DIR

1A

OUT

4

PFD

5

PWM

1

RC

AGND

REF

2

RC

LOGIC

10

2A

OUT

11

MS

2

12

MS

1

13

2

14 15

TIMER

6

7

8

÷8

9

V

DD

TRANSLATOR

& CONTROL LOGIC

REG

LOAD

V

BB1

28

SUPPLY

SLEEP

27

26

ENABLE

OUT

25

CP

24

CP

23

V

22

CHARGE PUMP

PGND

21

V

20

STEP

19

18

OUT

RESET

17

16

SR

LOAD

V

BB2

SUPPLY

Dwg. PP-075

CP

REG

1

SUFFIX '–LP', RθJA = 28°C/W*

4.0

1B

2

1

3.0

SUFFIX '–LP',

θJA = 33°C/W†

R

SUFFIX '–ED', RθJA = 32°C/W†

2.0

1.0

2B

0

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

25

2

Package Thermal Resistance, R

A3977xLP ......................... 28°C/W

A3977xED ........................ 32°C/W

A3977xLP ......................... 33°C/W

SUFFIX 'S–'

SUFFIX 'K–'

50 75 100 125 150

AMBIENT TEMPERATURE IN °°°°C

Dwg. GP-018-2A

θJA

*
†
†

* Measured on JEDEC standard “High-K” four-layer board.
† Measured on typical two-sided PCB with three square inches

2

(1935 mm

) copper ground area.

www.allegromicro.com

Table 1. Microstep Resolution Truth Table

MS

1

MS

2

Resolution

L L Full step (2 phase)

H L Half step

L H Quarter step

H H Eighth step

3

3977

MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

ELECTRICAL CHARACTERISTICS at T

= +25°C, V

A

= 35 V, VDD = 3.0 V to 5.5V (unless otherwise

BB

noted)

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Output Drivers

Load Supply Voltage Range V

BB

Operating 8.0 – 35 V

During sleep mode 0 – 35 V

Output Leakage Current I

Output On Resistance r

DS(on)

Body Diode Forward Voltage V

DSS

V

= V

OUT

V

OUT

Source driver, I

Sink driver, I

Source diode, IF = -2.5 A – – 1.4 V

F

BB

= 0 V – <1.0 -20 µA

= -2.5 A

OUT

= 2.5 A – 0.36 0.43 Ω

OUT

– <1.0 20 µA

– 0.45 0.57 Ω

Sink diode, IF = 2.5 A – – 1.4 V

Motor Supply Current I

BB

f

< 50 kHz – – 8.0 mA

PWM

Control Logic

Logic Supply Voltage Range V

Logic Input Voltage V

V

Logic Input Current I

I

Maximum STEP Frequency f

HOME Output Voltage V

Blank Time t

BLANK

Fixed Off Time t

DD

IN(1)

IN(0)

IN(1)

IN(0)

STEP

OH

V

OL

off

Operating, outputs disabled

– – 6.0 mA

Sleep mode – – 20 µA

Operating 3.0 5.0 5.5 V

VIN = 0.7V

VIN = 0.3V

DD

DD

0.7V

DD

– – 0.3V

-20 <1.0 20 µA

-20 <1.0 20 µA

––V

DD

V

500* – – kHz

I

= -200 µA 0.7V

OH

I

= 200 µA – – 0.3V

OL

R

= 56 kΩ, C

t

R

= 56 kΩ, Ct = 680 pF 30 38 46 µs

t

= 680 pF 700 950 1200 ns

t

DD

– – V

DD

V

continued next page …

4

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

3977

MICROSTEPPPING DMOS DRIVER

WITH TRANSLATOR

ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise
noted)

Limits

Characteristic Symbol Test Conditions

Control Logic (cont’d)

Mixed Decay Trip Point PFDH – 0.6V

PFDL – 0.21V
Ref. Input Voltage Range V
Reference Input Current I
Gain (Gm) Error

E

(note 3)

Crossover Dead Time t
Thermal Shutdown Temp. T
Thermal Shutdown Hysteresis ∆T
UVLO Enable Threshold V

UVLO

UVLO Hysteresis ∆V
Logic Supply Current I

Operating 0 – V

REF

REF

V

G

DT

J

J

UVLO

DDfPWM

= 2 V, Phase Current = 38.27% – – ±10 %

REF

V

= 2 V, Phase Current = 70.71% – – ±5.0 %

REF

= 2 V, Phase Current = 100.00% – – ±5.0 %

V

REF

SR enabled 100 475 800 ns

Increasing V

DD

< 50 kHz – – 12 mA
Outputs off – – 10 mA
Sleep mode – – 20 µA

* Operation at a step frequency greater than the specifi ed minimum value is possible but not warranteed.
NOTES: 1. Typical Data is for design information only.

2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.

3. EG = ([V

REF

/8] – V

SENSE

)/(V

REF

/8)

Min. Typ. Max. Units

DD

DD

–V
–V

DD

– 0 ±3.0 µA

– 165 – °C
–15 –°C

2.45 2.7 2.95 V

0.05 0.10 – V

V

www.allegromicro.com

5

3977

MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Functional Description

Device Operation. The A3977 is a complete

microstepping motor driver with built in translator for
easy operation with minimal control lines. It is designed
to operate bipolar stepper motors in full-, half-, quarter­and eighth-step modes. The current in each of the two
output H-bridges, all n-channel DMOS, is regulated with
fixed off time pulse-width modulated (PWM) control
circuitry. The H-bridge current at each step is set by the
value of an external current sense resistor (R
voltage (V

), and the DAC’s output voltage controlled

REF

), a reference

S

by the output of the translator.

At power up, or reset, the translator sets the DACs and
phase current polarity to initial home state (see figures for
home-state conditions), and sets the current regulator for
both phases to mixed-decay mode. When a step command
signal occurs on the STEP input the translator automati­cally sequences the DACs to the next level (see table 2 for
the current level sequence and current polarity). The
microstep resolution is set by inputs MS

and MS2 as

1

shown in table 1. If the new DAC output level is lower
than the previous level the decay mode for that H-bridge
will be set by the PFD input (fast, slow or mixed decay).
If the new DAC level is higher or equal to the previous
level then the decay mode for that H-bridge will be slow
decay. This automatic current-decay selection will
improve microstepping performance by reducing the
distortion of the current waveform due to the motor
BEMF.

Reset Input (RESET). The RESET input (active low)
sets the translator to a predefined home state (see figures
for home state conditions) and turns off all of the DMOS
outputs. The HOME output goes low and all STEP inputs
are ignored until the RESET input goes high.

Home Output (HOME). The HOME output is a logic
output indicator of the initial state of the translator. At
power up the translator is reset to the home state (see
figures for home state conditions).

Step Input (STEP). A low-to-high transition on the
STEP input sequences the translator and advances the
motor one increment. The translator controls the input to
the DACs and the direction of current flow in each wind­ing. The size of the increment is determined by the state
of inputs MS

Microstep Select (MS

and MS2 (see table 1).

1

and MS2). Input terminals

1

MS1 and MS2 select the microstepping format per
table 1. Changes to these inputs do not take effect until
the STEP command (see figure).

Direction Input (DIR). The state of the DIRECTION
input will determine the direction of rotation of the motor.

Internal PWM Current Control. Each H-bridge is
controlled by a fixed off time PWM current-control circuit
that limits the load current to a desired value (I

TRIP

).
Initially, a diagonal pair of source and sink DMOS outputs
are enabled and current flows through the motor winding
and RS. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense com­parator resets the PWM latch, which turns off the source
driver (slow-decay mode) or the sink and source drivers
(fast- or mixed-decay modes).

The maximum value of current limiting is set by the

selection of R

and the voltage at the V

S

input with a

REF

transconductance function approximated by:

max = V

I

TRIP

The DAC output reduces the V

REF

/8R

REF

S

output to the
current-sense comparator in precise steps (see table 2 for
% I

max at each step).

TRIP

= (% I

I

TRIP

max/100) x I

TRIP

TRIP

max

It is critical to ensure that the maximum rating (0.5 V)
on the SENSE terminal is not exceeded. For full-step
mode, V
VDD, because the peak sense value is 0.707 x V
all other modes V

can be applied up to the maximum rating of

REF

REF

should not exceed 4 V.

REF

/8. In

6

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]