Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature of 150°C.
...................... ±1.0 A
OUT
..................... 3 V
REF
DUAL DMOS FULL-BRIDGE MICRO-
STEPPING PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of
bipolar microstepping stepper motors, the A3973SB and A3973SLB are
capable of continuous output currents to ±1 A and operating voltages to
35 V. Internal fixed off-time PWM current-control timing circuitry can
be programmed via a serial interface to operate in slow, fast, and mixed
current-decay modes. The A3973SB (DIP) and the A3973SLB (SOIC)
are electrically identical and differ only in package style.
The desired load-current level is set via the serial port with two 6-bit
linear DACs in conjunction with a reference voltage. The six bits of
control allow maximum flexibility in torque control for a variety of step
methods, from microstepping to full-step drive. Load current is set in
1.56% increments of the maximum value.
Synchronous rectification circuitry allows the load current to flow
r
through the low
decay. This feature will eliminate the need for external clamp diodes in
most applications, saving cost and external component count, while
minimizing power dissipation.
Internal circuit protection includes thermal shutdown with hysteresis, transient-suppression diodes, and crossover-current protection.
Special power-up sequencing is not required.
The A3973SB is supplied in a 24-lead plastic DIP with a copper
batwing power tab; the A3973SLB is supplied in a 24-lead plastic SOIC
with a copper batwing power tab for surface-mount applications. The
power tabs are at ground potential and need no electrical isolation.
FEATURES
■ ±1 A, 35 V Continuous Output Rating
■ Low r
■ Optimized Microstepping via 6-Bit Linear DACs
■ Programmable Mixed, Fast, and Slow Current-Decay Modes
■ 4 MHz Internal Oscillator for Digital Timing
■ Serial-Interface Controls Chip Functions
■ Synchronous Rectification for Low Power Dissipation
■ Internal UVLO and Thermal Shutdown Circuitry
■ Crossover-Current Protection
■ Precision 2 V Reference
■ Inputs Compatible with 3.3 V or 5 V Control Signals
■ Sleep and Idle Modes
Always order by complete part number, e.g., A3973SB .
DMOS Output Drivers
DS(on)
of the DMOS output driver during the current
DS(on)
3973
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
Serial Interface. The A3973SB/SLB is controlled via a
3-wire (clock, data, strobe) serial port. The programmable
functions allow maximum flexibility in configuring the PWM to
the motor drive requirements. The serial data is written as two
19-bit words: 1 bit to select the word and 18 bits of data. The
serial data is clocked in starting with D18.
Word 0 Bit Assignments
BitFunction
D0Word select = 0
D1Bridge 1, DAC, LSB
D2Bridge 1, DAC, bit 2
D3Bridge 1, DAC, bit 3
D4Bridge 1, DAC, bit 4
D5Bridge 1, DAC, bit 5
D6Bridge 1, DAC, MSB
D7Bridge 2, DAC, LSB
D8Bridge 2, DAC, bit 2
D9Bridge 2, DAC, bit 3
D10Bridge 2, DAC, bit 4
D11Bridge 2, DAC, bit 5
D12Bridge 2, DAC, MSB
D13Bridge 1 phase
D14Bridge 2 phase
D15Bridge 1 mode
D16Bridge 2 mode
D17REF select
D18Range select
D1 – D6 Bridge 1 Linear DAC. Six-bit word sets desired
current level for Bridge 1. Setting all six bits to zero disables
Bridge 1, with all drivers off (See current regulation section of
functional description).
D7 – D12 Bridge 2 Linear DAC. Six-bit word sets desired
current level for Bridge 2. Setting all six bits to zero disables
Bridge 2, with all drivers off (See current regulation section of
functional description).
D13 Bridge 1 Phase. This bit controls the direction of
output current for Load 1.
D13OUT
1A
OUT
1B
0LH
1HL
D14 Bridge 2 Phase. This bit controls the direction of
output current for Load 2.
D14OUT
2A
OUT
2B
0LH
1HL
D15 Bridge 1 Mode.
D15Mode
0Mixed-decay
1Slow-decay
D16 Bridge 2 Mode.
D16Mode
0Mixed-decay
1Slow-decay
D17 REF Select. This bit determines the reference input for
the 6-bit linear DACs.
D17Reference Voltage
0Internal 2 V
1External (3 V max)
D18 Gm Range Select. This bit determines the scaling factor
(4 or 8) used.
D18DividerLoad Current
01/8 I
11/4 I
TRIP
TRIP
= V
= V
DAC
DAC
/8R
/4R
S
S
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continued next page ...
5
3973
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Word 1 Bit Assignments
BitFunction
D0Word select = 1
D1Blank-time LSB
D2Blank-time MSB
D3Off-time LSB
D4Off-time bit 1
D5Off-time bit 2
D6Off-time bit 3
D7Off-time MSB
D8Fast-decay time LSB
D9Fast-decay time bit 1
D10Fast-decay time bit 2
D11Fast-decay time MSB
D12C0 oscillator control
D13C1 oscillator control
D14SR control bit 1
D15SR control bit 2
D16Reserved for testing
D17Reserved for testing
D18Idle mode
D1 – D2 Blank Time. These two bits set the blank time for
the current-sense comparator. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents of the
clamp diodes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike from
erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time
counter to provide the programmable blanking function. The
blank timer is reset when PHASE is changed.
D2D1Time
004/f
016/f
108/f
1112/f
OSC
OSC
OSC
OSC
D3 – D7 Fixed Off Time. These five bits set the fixed off-
time for the internal PWM control circuitry. Fixed off-time is
defined by:
t
= [(1 + N) x 8/f
off
OSC
] - 1/f
OSC
where N = 0….31
For example, with a master oscillator frequency of 4 MHz, the
fast-decay time will be adjustable from 1.75 µs to 63.75 µs in
increments of 2 µs.
D8 – D11 Fast Decay Time. These four bits set the fastdecay portion of fixed off-time for the internal PWM control
circuitry. The fast-decay portion is defined by:
tfd = [(1 + N) x 8/f
OSC
] - 1/f
OSC
where N = 0….15
For example, with an oscillator frequency of 4 MHz, the fastdecay time will be adjustable from 1.75 µs to 31.75 µs in
increments of 2 µs. For t
> t
, the device will effectively
fd
off
operate in fast-decay mode.
D12 – D13 Oscillator Control. A 4 MHz internal oscillator
is used for the timing functions and charge-pump clock. If
more precise control is required, an external oscillator can be
input to the OSC terminal. To accommodate a wider range of
system clocks, an internal divider is provided to generate the
desired MO frequency according to the following table:
The different modes of operation are in the synchronous
rectification section of the functional description.
D16, D17. These bits are reserved for testing and should be
programmed to zero during normal operation.
D18 Idle Mode. The device can be placed in a low power“idle” mode by writing a “0” to D18. The outputs will be
disabled, the charge pump will be turned off, and the device
will draw a lower load supply currrent. The undervoltage
monitor circuit will remain active. D18 should be programmed
high for 1 ms before attempting to enable any output driver.
. This internally generated supply voltage is used to run
V
REG
the sink-side DMOS outputs. V
in the case of a fault condition, the outputs of the device are
disabled. The V
pin should be decoupled with a 0.22 µF
REG
capacitor to ground.
is internally monitored and
REG
3973
DUAL DMOS FULL-BRIDGE
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on V
CP
or V
device are disabled until the fault condition is removed. At
power up, or in the event of low VDD, the UVLO circuit
disables the drivers and resets the data in the serial port to zeros.
, the outputs of the
REG
Current Regulation. The reference voltage can be set by
analog input to the REF terminal, or via the internal 2 V
precision reference. The choice of reference voltage and sense
resistor set the maximum trip current.
I
TRIPMAX
= V
/(Range x RS)
REF
Microstepping current levels are set according to the following
equations:
I
= V
TRIP
V
= [(1 + DAC) x V
DAC
/(Range x RS)
DAC
REF
]/64
where DAC input code equals 1 to 63 and Range is 4 or 8 as
selected by Word 0, D18. Programming the DAC input code to
zero disables the bridge, and results in minimum load current.
PWM Timer Function. The PWM timer is programmable via
the serial port to provide fixed off-time PWM signals to the
control block. In mixed-decay mode, the first portion of the off
time operates in fast decay, until the fast-decay time count is
reached, followed by slow decay for the rest of the fixed offtime period. If the fast-decay time is set longer than the offtime, the device effectively operates in fast-decay mode.
Oscillator. The PWM timer is based on an oscillator input,
typically 4 MHz. The A3973SB/SLB can be configured to
select either a 4 MHz internal oscillator or, if more precision is
required, an external clock can be connected to the OSC
terminal. If an external clock is used, three internal divider
choices are selectable via the serial port to allow flexibility in
choosing f
, based on available system clocks. If the internal
OSC
oscillator option is used, the absolute accuracy is dependent on
the process variation of resistance and capacitance. A precision
resistor can be connected from the OSC terminal to VDD to
further improve the tolerance. The frequency will be:
f
= 204 x 109/R
OSC
OSC
If the internal oscillator is used without the external resistor, the
OSC terminal should be connected to ground.
Synchronous Rectification. When a PWM off-cycle is
triggered, either by a bridge disable command or internal fixed
off-time cycle, the load current will recirculate according to the
decay mode selected by the control logic. The A3973SB/SLB
synchronous rectification feature will turn on the appropriate
MOSFET(s) during the current decay and effectively short out
the body diodes with the low r
driver. This will lower
DS(on)
power dissipation significantly and can eliminate the need for
external Schottky diodes for most applications.
Four distinct modes of operation can be configured with the two
serial port control bits:
1. Active Mode. Prevents reversal of load current by
turning off synchronous rectification when a zero current
level is detected.
2. Passive Mode. Allows reversal of current but will turn
off the synchronous rectifier circuit if the load current
inversion ramps up to the current limit.
3. Disabled. MOSFET switching will not occur during load
recirculation. This setting would only be used with four
external clamp diodes per bridge.
4. Low Side Only. The low-side MOSFETs will switch on
during the off time to short out the current path through the
MOSFET body diode. With this setting, the high-side
MOSFETs will not synchronously rectify so four external
diodes from output to supply are recommended. This mode
is intended for use with high-power applications where it is
desired to save the expense of two external diodes per
bridge. In this mode, the sink-side MOSFETs are chopped
during the PWM off time. In all other cases, the sourceside MOSFETs are chopped in response to a PWM off
command.
Sleep Mode. The input terminal SLEEP is dedicated to
putting the device into a minimum current draw mode. When
pulled low, the serial port will be reset to all zeros and all
circuits will be disabled.
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7
3973
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
APPLICATIONS INFORMATION
Current Sensing. To minimize inaccuracies in sensing the
I
current level caused by ground-trace IR drops, the sense
PEAK
resistor should have an independent ground return to the ground
terminal of the device. For low-value sense resistors, the IR
drops in the sense resistor’s PCB traces can be significant and
should be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their
contact resistance.
Thermal Protection. Circuitry turns off all drivers when the
junction temperature reaches 165°C typically. It is intended
only to protect the device from failures due to excessive
junction temperature and should not imply that output short
circuits are permitted. Thermal shutdown has a hysteresis of
approximately 15°C.
Serial Port Write Timing Operation. Data is clocked into a
shift register on the rising edge of CLOCK signal. Normally,
STROBE will be held high, and only will be brought low to
initiate a write cycle. The data is written MSB first, followed
by the word-select bit. Refer to serial port diagram for timing
requirements.
SLEEP
Layout. The printed wiring board should use a heavy ground
plane. For optimum electrical and thermal performance, the
driver should be soldered directly onto the board. The ground
side of RS should have an individual path to the ground pin(s) of
the driver. This path should be as short as physically possible
and should not have any other components connected to it. The
load supply pin, VBB, should be decoupled with an electrolytic
capacitor (>47 µF is recommended) placed as close to the driver
as is possible.
H
STROBE
E
CLOCK
A
B
DATA
D18D0
A. Minimum Data Setup Time ..................................... 15 ns
B. Minimum Data Hold Time ...................................... 10 ns
C. Minimum Setup Strobe to Clock Rising Edge ...... 150 ns
D. Minimum Clock High Pulse Width......................... 40 ns
E. Minimum Clock Low Pulse Width ......................... 40 ns
F. Minimum Setup Clock Rising Edge to Strobe ........ 50 ns
G. Minimum Strobe Pulse Width............................... 150 ns
H. Minimum Setup Sleep to Strobe falling ................. 50 µs
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
11
3973
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER