ALLEGRO 3959 DATA SHEET

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3959

DMOS FULL-BRIDGE PWM

29319.37E

MOTOR DRIVER

Data Sheet

A3959SLB (SOIC)

Designed for pulse-width modulated (PWM) current control of dc
motors, the A3959SB, A3959SLB, and A3959SLP are capable of
output currents to ±3 A and operating voltages to 50 V. Internal fixed

V

24

REG

23

SLEEP

NO

NC

22

CONNECTION

21

B

OUT

V

20

LOAD SUPPLY

BB

19

GROUND

18

GROUND

SENSE

17

A

OUT

16

NO

NC

15

CONNECTION

EXT MODE

14

REF

13

Dwg. PP-069-4

CP

PHASE

ROSC

GROUND

GROUND

LOGIC SUPPLY

ENABLE

PFD

BLANK

PFD

CP

1

2

2

CP

1

3

4

5

6

7

8

9

9

2

10

11

1

12

θ

V

DD

CHARGE PUMP

LOGIC

÷

10

PWM TIMER

Note that the A3959SLB(SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do

not share a common

terminal assignment.

off-time PWM current-control timing circuitry can be adjusted via
control inputs to operate in slow, fast, and mixed current-decay modes.

PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.

Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.

The A3959SB/SLB/SLP is a choice of three power packages, a
24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), a
24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’),
and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal
pad (suffix ‘LP’). In all cases, the power tab is at ground potential and
needs no electrical isolation.

free version (100% matte tin leadframe).

ABSOLUTE MAXIMUM RATINGS

Load Supply Voltage, VBB......................... 50 V

Output Current, I

(Repetitive) ........... ±3.0 A

OUT

(Peak, <3 µs) ................................... ±6.0 A

Logic Supply Voltage, VDD....................... 7.0 V

Logic Input Voltage Range, V

IN

(Continuous) ............ -0.3 V to VDD + 0.3 V

<30 ns) ............... -1.0 V to VDD + 1.0 V

(t

w

Sense Voltage, VS (Continuous) .............. 0.5 V

(tw <3 µs) ........................................... 2.5 V

Reference Voltage, V
Package Power Dissipation (TA = 25°C), P

............................ V

REF

DD

D

A3959SB ........................................ 3.3 W*

A3959SLB ...................................... 2.5 W*

A3959SLP ...................................... 3.1 W*

Operating Temp. Range, T

.... -20°C to +85°C

A

Junction Temperature, TJ..................... +150°C

Storage Temp. Range, TS..... -55°C to +150°C

Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.

* Double-sided board, one square inch copper each side. See also, Layout, page 7.

FEATURES

■ ±3 A, 50 V Output Rating

■ Low

■ Mixed, Fast, and Slow Current-Decay Modes

■ Synchronous Rectification for Low Power Dissipation

■ Internal UVLO and Thermal-Shutdown Circuitry

■ Crossover-Current Protection

■ Internal Oscillator for Digital PWM Timing

Always order by complete part number:

Part Number Package R

A3959SB-T 24-pin batwing DIP; Lead-free 38°C/W 6°C/W

A3959SLB 24-lead batwing SOIC 50°C/W 6°C/W

A3959SLB-T 24-lead batwing SOIC; Lead-free 50°C/W 6°C/W

A3959SLP 28-lead thin shrink SOIC 40°C/W —

A3959SLP-T 28-lead thin shrink SOIC; Lead-free 40°C/W —

r

Outputs (270 mΩ, Typical)

DS(on)

A3959SB 24-pin batwing DIP 38°C/W 6°C/W

Each package is available in a lead-

* R

θθ

θJA

θθ

θθ

θJT

θθ

3959

DMOS FULL-BRIDGE
PWM MOTOR DRIVER

V

DD

LOGIC

SUPPLY

FUNCTIONAL BLOCK DIAGRAM

VBB

CP1

CP2

CP

LOAD
SUPPLY

+

SLEEP

EXT MODE

PHASE

ENABLE

TO VDD

BLANK

PFD1
PFD2

ROSC

CHARGE PUMP

CP

PHASE

2

1

BANDGAP

V

C

REG

TSD

1

2

θ

3

VOLTAGE &

DD

FAULT DETECT

CONTROL LOGIC

PWM

TIMER

OSC

CHARGE PUMP

UNDER-

CHARGE

PUMP

BANDGAP

REGULATOR

VREG

OUTA

GATE DRIVE

OUTB

SENSE

ZERO

CURRENT

DETECT

CURRENT

SENSE

CPCP

24

REG

V

23

SLEEP

22

REFERENCE

BUFFER &

÷10

REF

CS

RS

V

Dwg. FP-048-2A

REF

ROSC

GROUND

GROUND

GROUND

GROUND

LOGIC

SUPPLY
ENABLE

BLANK

2

PFD

4

5

6

7

8

9

V

9

10

2

11

12

LOGIC

DD

PWM TIMER

V

BB

÷

10

21

20

19

18

17

16

15

14

13

OUT

B

LOAD
SUPPLY

GROUND

GROUND

SENSE

OUT

A

EXT MODE

REF

PFD

1

Dwg. PP-069-5A

A3959SB (DIP)

Note that the A3959SLB (SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do
terminal assignment.

not share a common

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 2001, 2003 Allegro MicroSystems, Inc.

3959

DMOS FULL-BRIDGE

PWM MOTOR DRIVER

ELECTRICAL CHARACTERISTICS at T
f

< 50 kHz (unless noted otherwise)

PWM

= +25°C, V

A

= 50 V, VDD = 5.0 V, V

BB

SENSE

= 0.5 V,

Limits

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Output Drivers

Load Supply Voltage Range V

BB

Operating 9.5 – 50 V

During sleep mode 0 – 50 V

Output Leakage Current I

Output On Resistance r

DSS

DS(on)

V

= V

OUT

V

OUT

Source driver, I

Sink driver, I

BB

= 0 V – <-1.0 -20 µA

= -3 A – 270 300 mΩ

OUT

= 3 A – 270 300 mΩ

OUT

– <1.0 20 µA

Crossover Delay 300 600 1000 ns

Body Diode Forward Voltage V

Source diode, IF = -3 A – – 1.6 V

F

Sink diode, IF = 3 A – – 1.6 V

Load Supply Current I

BB

f

< 50 kHz – 4.0 7.0 mA

PWM

Charge pump on, outputs disabled – 2.0 5.0 mA

Control Logic

Logic Supply Voltage Range V

Logic Input Voltage V

V

Logic Input Current I
(all inputs except ENABLE)

I

ENABLE Input Current I

I

Internal OSC frequency f

Reference Input Volt. Range V

Reference Input Current I

Comparator Input Offset Volt. V

DD

IN(1)

IN(0)

IN(1)

IN(0)

IN(1)

IN(0)

OSC

REF

REF

IO

Sleep Mode – – 20 µA

Operating 4.5 5.0 5.5 V

2.0 – – V

– – 0.8 V

V

= 2.0 V – <1.0 20 µA

IN

V

= 0.8 V – <-2.0 -20 µA

IN

V

= 2.0 V – 40 100 µA

IN

V

= 0.8 V – 16 40 µA

IN

R

shorted to GROUND 3.25 4.25 5.25 MHz

OSC

R

= 51 kΩ 3.65 4.25 4.85 MHz

OSC

Operating 0.0 – V

V

= V

V

REF

REF

DD

= 0 V – ±5.0 – mV

––±1.0 µA

Continued next page …

DD

V

www.allegromicro.com

3

3959

DMOS FULL-BRIDGE
PWM MOTOR DRIVER

ELECTRICAL CHARACTERISTICS at T
f

< 50 kHz (unless noted otherwise), continued.

PWM

= +25°C, V

A

= 50 V, VDD = 5.0 V, V

BB

SENSE

= 0.5 V,

Limits

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Control Logic

Reference Divider Ratio – – 10 – –

Gm Error E

Gm

(Note 3) V

Propagation Delay Times t

pd

V

= V

REF

REF

0.5 Ein to 0.9 E

DD

= 0.5 V – – ±14 %

:

out

––±4.0 %

PWM change to source on 600 750 1200 ns
PWM change to source off 50 150 350 ns
PWM change to sink on 600 750 1200 ns
PWM change to sink off 50 100 150 ns

Thermal Shutdown Temp. T

Thermal Shutdown Hysteresis ∆T

J

J

UVLO Enable Threshold UVLO Increasing V

DD

– 165 – °C
–15– °C

3.90 4.2 4.45 V

UVLO Hysteresis ∆UVLO 0.05 0.10 – V

Logic Supply Current I

DD

f

< 50 kHz – 6.0 10 mA

PWM

Sleep Mode – – 2.0 mA

NOTES: 1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device terminal.

3. Gm error = ([V

4

/10] – V

REF

SENSE

)/(V

REF

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

/10) where V

SENSE

= I

TRIP•RS

.