Note the A3955SB (DIP) and the A3955SLB
(SOIC) are electrically identical and share a
common terminal number assignment.
4
5
6
V
CC
7
D
8
2
LOGIC
V
BB
LOAD
16
SUPPLY
OUT
15
D
14
GROUND
13
12
GROUND
11
SENSE
OUT
10
9
D
Dwg. PP-056-2
Data Sheet
29319.41
3955
FULL-BRIDGE PWM
MICROSTEPPING MOTOR DRIVER
The A3955SB and A3955SLB are designed for driving one winding
of a bipolar stepper motor in a microstepping mode. The outputs are
rated for continuous output currents to ±1.5 A and operating voltages
B
0
A
1
to 50 V. Internal pulse-width modulated (PWM) current control combined with an internal three-bit nonlinear digital-to-analog converter
allows the motor current to be controlled in full-, half-, quarter-, or
eighth-step (microstepping) modes. Nonlinear increments minimize
the number of control lines necessary for microstepping.
Microstepping provides for increased step resolution, and reduces
torque variations and resonance problems at low speed.
Internal circuitry determines whether the PWM current-control
circuitry operates in a slow (recirculating) current-decay mode, fast
(regenerative) current-decay mode, or in a mixed current-decay mode
in which the off time is divided into a period of fast current decay with
the remainder of the fixed off time spent in slow current decay. The
combination of user-selectable current-sensing resistor and reference
voltage, digitally selected output current ratio; and slow, fast, or mixed
current-decay modes provides users with a broad, variable range of
motor control.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB. . . . . . . . . . 50 V
Output Current, I
(Continuous) . . . . . . . . . . . . . . ±1.5 A*
Logic Supply Voltage, V
Logic/Reference Input Voltage Range,
V
. . . . . . . . . . . -0.3 V to VCC + 0.3 V
IN
Sense Voltage, V
Package Power Dissipation,
P
. . . . . . . . . . . . . . . . . . . . See Graph
D
Operating Temperature Range,
T
. . . . . . . . . . . . . . . . . -20˚C to +85˚C
A
Junction Temperature, T
Storage Temperature Range,
T
. . . . . . . . . . . . . . . . -55˚C to +150˚C
S
* Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150˚C.
† Fault conditions that produce excessive junction
temperature will activate the device’s thermal
shutdown circuitry. These conditions can be
tolerated but should be avoided.
OUT
. . . . . . . . . 7.0 V
CC
. . . . . . . . . . . . . . . . 1.0 V
S
. . . . . . . +150˚C†
J
Internal circuit protection includes thermal shutdown with hysteresis, transient-suppression diodes, and crossover current protection.
Special power-up sequencing is not required.
The A3955S— is supplied in a choice of two power packages; a
16-pin dual-in-line plastic package with copper heat-sink tabs (suffix
‘B’), and a 16-lead plastic SOIC with copper heat-sink tabs (suffix ‘LB’).
For both package styles, the power tab is at ground potential and
needs no electrical isolation.
FEATURES
■ ±1.5 A Continuous Output Current
■ 50 V Output Voltage Rating
■ Internal PWM Current Control
■ 3-Bit Non-Linear DAC
■ Fast, Mixed Fast/Slow, and Slow Current-Decay Modes
1PFD(Percent Fast Decay) The analog input used to set the current-decay mode.
2REF(V
3RCThe parallel combination of external resistor RT and capacitor CT set the off time for the
4-5GROUNDReturn for the logic supply (VCC) and load supply (VBB); the reference for all voltage
6LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V.
7PHASEThe PHASE input determines the direction of current in the load.
8D2(DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter.
9D1(DATA1) One-of-three control bits for the internal digital-to-analog converter.
10OUT
11SENSEConnection to the sink-transistor emitters. Sense resistor RS is connected between this
12-13GROUNDReturn for the logic supply (VCC) and load supply (VBB); the reference for all voltage
14D
15OUT
16LOAD SUPPLY(VBB) Supply voltage for the load.
A
0
B
) The voltage at this input (along with the value of RS and the states of DAC inputs
REF
D0, D1, and D2) set the peak output current.
PWM current regulator. CT also sets the blanking time.
measurements.
One-of-two output load connections.
point and ground.
measurements.
(DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter.
One-of-two output load connections.
Two A3955S— full-bridge PWM microstepping motor
drivers are needed to drive the windings of a bipolar
stepper motor. Internal pulse-width modulated (PWM)
control circuitry regulates each motor winding’s current.
The peak motor current is set by the value of an external
current-sense resistor (RS), a reference voltage (V
and the digital-to-analog converter (DAC) data inputs (D0,
D1, and D2).
To improve motor performance, especially when using
sinusoidal current profiles necessary for microstepping,
the A3955S— has three distinct current-decay modes:
slow decay, fast decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of
current flow in the load (table 1). An internally generated
dead time of approximately 1 µs prevents crossover
currents that could occur when switching the PHASE
input.
DAC Data Inputs (D0, D1, D2). A non-linear DAC is used
to digitally control the output current. The output of the
DAC is used to set the trip point of the current-sense
comparator. Table 3 shows DAC output voltages for each
input condition. When D0, D1, and D2 are all logic low, all
of the power output transistors are turned off.
Internal PWM Current Control. Each motor driver
contains an internal fixed off-time PWM current-control
circuit that limits the load current to a desired value (I
Initially, a diagonal pair of source and sink transistors are
enabled and current flows through the motor winding and
V
BB
DRIVE CURRENT
RECIRCULATION
(SLOW-DECAY MODE)
RECIRCULATION
(FAST-DECAY MODE)
R
S
Dwg. EP-006-15
REF
),
TRIP
RS (figure 1). When the voltage across the sense resistor
equals the DAC output voltage the current-sense comparator resets the PWM latch, which turns off the source
drivers (slow-decay mode) or the sink and source drivers
(fast- or mixed-decay mode).
With the DATA input lines tied to VCC, the maximum
value of current limiting is set by the selection of RS and
V
with a transconductance function approximated by:
REF
I
≈ V
TRIP
The actual peak load current (I
than I
due to internal logic and switching delays. The
TRIP
/3RS.
REF
) will be slightly higher
PEAK
driver(s) remain off for a time period determined by a
user-selected external resistor-capacitor combination
(RTCT). At the end of the fixed off time, the driver(s) are
re-enabled, allowing the load current to increase to I
again, maintaining an average load current.
The DAC data input lines are used to provide up to
eight levels of output current. The internal 3-bit digital-toanalog converter reduces the reference input to the
current-sense comparator in precise steps (the step
reference current ratio or SRCR) to provide half-step,
quarter-step, or “microstepping” load-current levels.
I
≈ SRCR x V
TRIP
Slow Current-Decay Mode. When V
REF
/3R
S
≥ 3.5 V, the
PFD
device is in slow current-decay mode (the source drivers
are disabled when the load current reaches I
the fixed off time, the load inductance causes the current
).
to recirculate through the motor winding, sink driver,
ground clamp diode, and sense resistor (see figure 1).
Slow-decay mode produces low ripple current for a given
fixed off time (see figure 2). Low ripple current is desirable because the average current in the motor winding is
more nearly equal to the desired reference value, resulting in increased motor performance in microstepping
applications.
For a given level of ripple current, slow decay affords
the lowest PWM frequency, which reduces heating in the
motor and driver IC due to a corresponding decrease in
hysteretic core losses and switching losses respectively.
Slow decay also has the advantage that the PWM load
current regulation can follow a more rapidly increasing
reference before the PWM frequency drops into the
audible range. For these reasons slow-decay mode is
typically used as long as good current regulation can be
maintained.
). During
TRIP
TRIP
Figure 1 — Load-Current Paths
3955
FULL-BRIDGE PWM
MICROSTEPPING
MOTOR DRIVER
Under some circumstances slow-decay mode PWM
can fail to maintain good current regulation:
1) The load current will fail to regulate in slow-decay
mode due to a sufficiently negative back-EMF voltage
in conjunction with the low voltage drop across the
load during slow decay recirculation. The negative
back-EMF voltage can cause the load current to
actually increase during the slow decay off time. A
negative back-EMF voltage condition commonly
occurs when driving stepping motors because the
phase lead of the rotor typically causes the back-EMF
voltage to be negative towards the end of each step
(see figure 3A).
2) When the desired load current is decreased rapidly,
the slow rate of load current decay can prevent the
current from following the desired reference value.
A — Slow-Decay
3) When the desired load current is set to a very low
value, the current-control loop can fail to regulate due
to its minimum duty cycle, which is a function of the
user-selected value of t
pulse width t
that occurs each time the PWM
on(min)
and the minimum on-time
OFF
latch is reset.
Fast Current-Decay Mode. When V
≤ 0.8 V, the
PFD
device is in fast current-decay mode (both the sink and
source drivers are disabled when the load current reaches
I
). During the fixed off time, the load inductance
TRIP
causes the current to flow from ground to the load supply
via the motor winding, ground-clamp and flyback diodes
(see figure 1). Because the full motor supply voltage is
across the load during fast-decay recirculation, the rate of
load current decay is rapid, producing a high ripple current
for a given fixed off time (see figure 2). This rapid rate of
decay allows good current regulation to be maintained at
the cost of decreased average current accuracy or
increased driver and motor losses.
Mixed Current-Decay Mode. If V
is between 1.1 V
PFD
and 3.1 V, the device will be in a mixed current-decay
mode. Mixed-decay mode allows the user to achieve
good current regulation with a minimum amount of ripple
current and motor/driver losses by selecting the minimum
percentage of fast decay required for their application
(see also Stepper Motor Applications).
As in fast current-decay mode, mixed-decay starts with
the sink and source drivers disabled after the load current
reaches I
decays to a value below V
. When the voltage at the RC terminal
TRIP
, the sink drivers are re-
PFD
enabled, placing the device in slow current-decay mode
for the remainder of the fixed off time (figure 2). The
percentage of fast decay (PFD) is user determined by
V
or two external resistors.
PFD
PFD = 100 ln (0.6[R1+R2]/R2)
where
V
CC
R
1
PFD
R
2
With increasing values of t
switching losses will
OFF,
decrease, low-level load-current regulation will improve,
EMI will be reduced, the PWM frequency will decrease,
and ripple current will increase. A value of t
OFF
can be
chosen for optimization of these parameters. For applications where audible noise is a concern, typical values of
t
are chosen to be in the range of 15 µs to 35 µs.
OFF
RC Blanking. In addition to determining the fixed off-time
of the PWM control circuit, the CT component sets the
comparator blanking time. This function blanks the output
of the current-sense comparator when the outputs are
switched by the internal current-control circuitry (or by the
PHASE input, or when the device is enabled with the DAC
data inputs). The comparator output is blanked to prevent
false over-current detections due to reverse recovery
currents of the clamp diodes, and/or switching transients
related to distributed capacitance in the load.
During internal PWM operation, at the end of the t
OFF
time, the comparator’s output is blanked and CT begins to
be charged from approximately 0.22VCC by an internal
current source of approximately 1 mA. The comparator
output remains blanked until the voltage on CT reaches
approximately 0.6VCC. The blanking time, t
BLANK
, can be
calculated as:
t
= RTCT ln (RT/[RT - 3 kΩ]).
BLANK
Dwg. EP-062-1
Fixed Off-Time. The internal PWM current-control
circuitry uses a one shot to control the time the driver(s)
remain(s) off. The one-shot off-time, t
, is determined by
OFF
the selection of an external resistor (RT) and capacitor (CT)
connected from the RC timing terminal to ground. The offtime, over a range of values of CT = 470 pF to 1500 pF
and RT = 12 kΩ to 100 kΩ, is approximated by:
t
≈ RTCT.
OFF
When the load current is increasing, but has not yet
reached the sense-current comparator threshold (I
TRIP
),
the voltage on the RC terminal is approximately 0.6VCC.
When I
is reached, the PWM latch is reset by the
TRIP
current-sense comparator and the voltage on the RC
terminal will decay until it reaches approximately 0.22VCC.
The PWM latch is then set, thereby re-enabling the
driver(s) and allowing load current to increase again. The
PWM cycle repeats, maintaining the peak load current at
the desired value.
When a transition of the PHASE input occurs, CT is
discharged to near ground during the crossover delay time
(the crossover delay time is present to prevent simultaneous conduction of the source and sink drivers). After
the crossover delay, CT is charged by an internal current
source of approximately 1 mA. The comparator output
remains blanked until the voltage on CT reaches approximately 0.6VCC.
Similarly, when the device is disabled, via the DAC
data inputs, CT is discharged to near ground. When the
device is re-enabled, CT is charged by an internal current
source of approximately 1 mA. The comparator output
remains blanked until the voltage on CT reaches approximately 0.6VCC. The blanking time, t
, can be calcu-
BLANK
lated as:
t
= RTCT ln ([RT - 1.1 kΩ]/RT - 3 kΩ).
BLANK
The minimum recommended value for CT is 470 pF
± 5 %. This value ensures that the blanking time is
sufficient to avoid false trips of the comparator under
3955
FULL-BRIDGE PWM
MICROSTEPPING
MOTOR DRIVER
normal operating conditions. For optimal regulation of the
load current, this value for CT is recommended and the
value of RT can be sized to determine t
OFF
.
Thermal Considerations. Thermal-protection circuitry
turns off all output transistors when the junction temperature reaches approximately +165°C. This is intended only
to protect the device from failures due to excessive
junction temperatures and should not imply that output
short circuits are permitted. The output transistors are reenabled when the junction temperature cools to approximately +150°C.
V
BRIDGE A
V
PFD
V
REF
1
2
3
BB
16
+
47 µF
15
14
D
0A
Stepper Motor Applications. The A3955SB or
A3955SLB are used to optimize performance in
microstepping/sinusoidal stepper-motor drive applications
(see figures 4 and 5). When the load current is increasing, the slow current-decay mode is used to limit the
switching losses in the driver and iron losses in the motor.
This also improves the maximum rate at which the load
current can increase (as compared to fast decay) due to
the slow rate of decay during t
. When the load current
OFF
is decreasing, the mixed current-decay mode is used to
regulate the load current to the desired level. This prevents tailing of the current profile caused by the back-EMF
voltage of the stepper motor (see figure 3A).
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Webbed lead frame. Leads 4, 5, 12, and 13 are internally one piece.
10.65
10.00
0° TO 8°
1.27
0.40
Dwg. MA-008-17A mm
3955
FULL-BRIDGE PWM
MICROSTEPPING
MOTOR DRIVER
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such
departures from the detail specifications as may be required to permit improvements in
the design of its products.
The information included herein is believed to be accurate and reliable. However,
Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.