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3946
Half-Bridge Power MOSFET Controller
Data Sheet
29319.150
A3946KLB SOIC
VREG
Scale 1:1
CP2
CP1
PGND
GH
BOOT
1
2
3
4
GL
5
S
6
7
8
16
15
14
13
12
11
10
9
VBB
VREF
DT
LGND
RESET
IN2
IN1
~FAULT
A3946KLP TSSOP with Exposed Thermal Pad
Scale 1:1
VREG
CP2
CP1
PGND
GH
BOOT
1
2
3
4
GL
5
S
6
7
8
16
15
14
13
12
11
10
9
VBB
VREF
DT
LGND
RESET
IN2
IN1
~FAULT
AB SO LUTE MAX I MUM RAT INGS
Load Supply Voltage, VBB............................. 60 V
Logic Inputs ..................................–0.3 V to 6.5 V
Pin S……..........................................–4 V to 60 V
Pin GH ...........................................–4 V to 75 V
Pin BOOT….. ................................–0.6 V to 75 V
Pin DT ........................................................ V
Pin VREG ......................................–0.6 V to 15 V
Package Thermal Resistance, R
JA
A3946KLB..................................... 48°C/W
A3946KLB..................................... 38°C/W
A3946KLP ..................................... 44°C/W
A3946KLP ..................................... 34°C/W
Operating Temperature Range, TA.. –40°C to +135°C
Junction Temperature, T
Storage Temperature Range, T
Notes:
1. Measured on a two-sided PCB with 3 in.
2 oz. copper.
2. Measured on JEDEC standard High-K board.
...........................+150°C
J
....-55°C to +150°C
S
2
REF
of
1
2
1
2
The A3946 is designed specifi cally for ap pli ca tions that require
high power unidirectional dc motors, three-phase brushless dc motors, or
other inductive loads. The A3946 provides two high-current gate drive
outputs that are capable of driving a wide range of power N-channel
MOSFETs. The high-side gate driver switches an N-channel MOSFET
that controls current to the load, while the low-side gate driver switches
an N-channel MOSFET as a synchronous rectifi er.
A bootstrap capacitor provides the above-battery supply voltage
required for N-channel MOSFETs. An internal charge pump for the
high side allows for dc (100% duty cycle) operation of the half-bridge.
The A3946 is available in a choice of two power pack ag es: a
16-lead
SOIC with copper batwing power tab (part number suffi x LB),
and a 16-lead TSSOP with ex posed thermal pad (suffi x LP).
FEATURES
On-chip charge pump for 7 V minimum input supply voltage
High-current gate drive for driving a wide range of
N-channel
MOSFETs
Bootstrapped gate drive with charge pump for 100% duty cycle
Overtemperature protection
Undervoltage protection
–40ºC to 135ºC ambient operation
Always order by complete part number:
Part Number Package
A3946KLB
A3946KLP
16-Lead SOIC; Copper Batwing Power Tab
16-Lead TSSOP; Exposed Thermal Pad
Half
-Bridge Power MOSFET Controller
Functional Block Diagram
+VBAT
3946
Data Sheet
29319.150
L
10
kΩ
VREF
R
DEAD
L
VREF
0.1 uF
X7R
10 V
~FAULT
DT
IN1
IN2
RESET
C2
0.47 uF, X7R
V rated to VBAT
P
+5 Vref
L
L
L
VBB
L
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Turn-On
Delay
P
Control
Logic
C1
0.47 uF, X7R
V rated to VBAT
Charge
Pump
Charge
Pump
Bootstrap
UVLO
CP1CP2
VREG
C
REG
I
LIM
High Side
Driver
Low Side
Driver
P
BOOT
GH
S
VREG
GL
PGND
LGND
L
P
C
BOOT
R
GATE
P
R
GATE
PL
Control Logic Table
IN1 IN2 DT Pin RESET GH GL Function
X X X 0 Z Z Sleep mode
00R
01R
10R
11R
- LGND 1 L H Low-side FET ON following dead time
DEAD
- LGND 1 L L All OFF
DEAD
- LGND 1 L L All OFF
DEAD
- LGND 1 H L High-side FET ON following dead time
DEAD
0 0 VREF 1 L L All OFF
0 1 VREF 1 L H Low-side FET ON
1 0 VREF 1 H L High-side FET ON
1 1 VREF 1 H H CAUTION: High-side and low-side FETs ON
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Half
3946
-Bridge Power MOSFET Controller
Data Sheet
29319.150
ELECTRICAL CHARACTERISTICS at T
= –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
A
Characteristics Symbol Test Conditions
VBB Quiescent Current I
VREG Output Voltage V
Charge Pump Frequency F
VREF Output Voltage V
VBB
REG
REF
RESET = High, Outputs Low
RESET = Low
V
> 7.75 V, I
BB
V
= 7 V to 7.75 V, I
BB
CP1, CP2
CP
I
≤ 4 mA, C
REF
= 0 mA to 15 mA 12.0 13 13.5 V
reg
= 0.1 µF 4.5
REF
Gate Output Drive
Turn On Time t
Turn Off Time t
Pullup On Resistance R
Pulldown On Resistance R
Short Circuit Current –
Source
Short Circuit Current –
Sink
GH Output Voltage V
GL Output Voltage V
DSDOWN
rise
fall
DSUP
–
–
C
= 3300 pF, 20% to 80%
LOAD
C
= 3300 pF, 80% to 20%
LOAD
Tj = 25°C
= 135°C
T
j
Tj = 25°C
= 135°C
T
j
tpw < 10 µs 800
tpw < 10 µs 1000
tpw < 10 µs, Bootstrap Capacitor fully charged V
GH
GL
Timing
R
Dead Time (Delay from
Turn Off to Turn On)
Propagation Delay t
t
DEAD
PD
= 5 kΩ 200 350 500 ns
dead
R
= 100 kΩ 567µs
dead
Logic input to unloaded GH, GL. DT = VREF
= 0 mA to 15 mA 11.0
reg
–
V
Limits
Min. Typ. Max. Units
–
––
–
–
–
–
–
–
–
– 1.5
REG
– 0.2
REG
––
36mA
10 µA
–
62.5
–
60 100 ns
40 80 ns
4
6
2
3
––
––
13.5 V
–
5.5 V
kHz
–
–
–
–
mA
mA
––
––
150 ns
Ω
Ω
Ω
Ω
V
V
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3
Half
3946
-Bridge Power MOSFET Controller
Data Sheet
29319.150
ELECTRICAL CHARACTERISTICS at T
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Protection
VREG Undervoltage V
VREG Undervoltage V
BOOT Undervoltage V
BOOT Undervoltage V
Thermal Shutdown Temperature T
Thermal Shutdown Hysteresis ∆T
REGON
REGOFF
BSOFF
Logic
Input Current I
I
Logic Input Voltage V
V
Logic Input Hysteresis
Fault Output
V
BSON
JTSD
IN(1)
IN(0)
IN(1)
IN(0)
–
V
ol
oh
V
REG
V
REG
V
BOOT
V
BOOT
Temperature increasing
Recovery = T
J
IN1 VIN / IN2 VIN = 2.0 V
IN1 VIN / IN2 VIN = 0.8 V
RESET pin only
IN1 / IN2 logic high 2.0
RESET logic high 2.2
Logic low
All digital inputs 100
I = 1 mA, fault asserted
V = 5 V
= –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
A
Limits
increasing 8.6 9.1 9.6 V
decreasing 7.8 8.3 8.8 V
increasing 8 8.75 9.5 V
decreasing 7.25 8.0 8.75 V
170
15
40 100 µA
16 40 µA
–
–
1 µA
JTSD
– ∆T
–
J
–
–
–
––
––
––
––
–
––
––
0.8 V
300 mV
400 mV
1 µA
°C
°C
V
V
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
Half
-Bridge Power MOSFET Controller
Functional Description
3946
Data Sheet
29319.150
VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side
gate drive.
The VREG capacitor, C
, must supply the instantaneous
REG
current to the gate of the low-side MOSFET. A 10 µF, 25 V
capacitor should be adequate. This capacitor can be either
electrolytic or ceramic (X7R).
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line
is high and any of the following conditions are present:
• Undervoltage conditions on VREG (UVREG) or on the
internal logic supply VREF (UVREF). These conditions
set a latched fault.
• A junction temperature > 170°C (OVERTEMP). This condition sets a latched fault.
• An undervoltage on the stored charge of the BOOT capacitor (UVBOOT). This condition does NOT set a latched
fault.
An overtemperature event signals a latched fault, but does
not disable any output drivers, regulators, or logic inputs.
The user must turn off the A3946 (e.g., force the RESET line
low) to prevent damage.
cleared immediately, and remains cleared. If the power is
restored (no UVREG or UVREF), and if no OVERTEMP
fault exists, then the latched fault remains cleared when the
RESET line returns to high. However, FAULT = 1 may still
occur because a UVBOOT fault condition may still exist.
Charge Pump. The A3946 is designed to ac com mo date
a wide range of power supply voltages. The charge pump
output, VREG, is regulated to 13 V nominal.
In all modes, this regulator is current-limited. When V
BB
< 8 V, the charge pump operates as a voltage doubler. When
8 V < VBB< 15 V, the charge pump operates as a voltage
doubler/PWM, current-controlled, voltage regulator. When
VBB>15 V, the charge pump operates as a PWM, current-controlled, voltage regulator. Effi ciency shifts, from 80% at VBB=
7 V, to 20% at VBB = 50 V.
CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
confi guration is NOT recommended. There is no assurance
that one of the regulators will not dominate, taking on all of
the load and back-biasing the other regulators. (For example,
this could occur if a particular regulator has an internal reference voltage that is higher that those of the other regulators,
which would force it to regulate at the highest voltage.)
The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.
Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create
a UVBOOT fault condition, which in turn inhibits the highside driver and creates a FAULT = 1. This fault is NOT
latched. To remove this fault, momentarily turn on GL to
charge the BOOT capacitor.
Latched faults may be cleared by a low pulse, 1 to 10 µs
wide, on the RESET line. Throughout that pulse (despite
a possible UVBOOT), FAULT = 0; also the fault latch is
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115 Northeast Cutoff, Box 15036
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Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is
high), the gate drive outputs stay disabled and a fault remains
asserted until VREF and VREG pass their undervoltage
thresholds. When powering up, before starting the fi rst boot-
strap charge cycle, wait until t = C
⁄ 4 (where C
REG
REG
is in
µF, and t is in ns) to allow the charge pump to stabilize.
When powered-up (not in Sleep Mode), if the RESET line
is low for > 10 µs, the A3946 may start to enter Sleep Mode
(V
< 4 V). In that case, ~FAULT = 1 as long as the RESET
REF
line remains low.
If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.
5
Half
3946
-Bridge Power MOSFET Controller
Data Sheet
29319.150
Dead Time. The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When in struct ed to
turn off, the gate outputs change after an short internal propagation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, t
, can be adjusted within the range 350 ns
DEAD
to 6000 ns using the following formula:
t
where t
is in ns, and R
DEAD
range 5 k < R
< 100 k.
DEAD
DEAD
= 50 + (R
is in , and should be in the
DEAD
DEAD
⁄ 16.7 )
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 µs.
Control Logic. Two different methods of control are
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Top-Off Charge Pump. An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount
of bias current (< 200 µA) is drawn from the BOOT pin
to operate the fl oating high-side circuit. The charge pump
simply provides enough drive to ensure that the gate voltage
does not droop due to this bias supply current. The charge
required for initial turn-on of the high-side gate must be supplied by bootstrap capacitor charge cycles. This is described
in the section Application Information.
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by shorting IN1 with IN2. If a very slow turn-on is required (greater
than 6 µs), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
Fault Response Table
Fault Mode RESET ~FAULT VREG VREF GH
No Fault 1 1 ON ON (IL) (IL)
BOOT Capacitor Undervoltage
VREG Undervoltage
VREF Undervoltage
Thermal Shutdown
5
Sleep
1
(IL) indicates that the state is determined by the input logic.
2
This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
3
These faults are latched. Clear by pulsing RESET = 0.
4
Unspecifi ed VREF undervoltage threshold < 4 V.
5
During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to be-
come high impedance (High Z). Refer to the section Sleep Mode/Power Up.
3
4
3
2
1 0 ON ON 0 (IL)
1 0 ON ON 0 0
1 0 OFF ON 0 0
1 0 ON ON (IL) (IL)
0 1 OFF OFF High Z High Z
VREF. VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 µF
capacitor is needed for decoupling.
1
GL
1
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
Half
-Bridge Power MOSFET Controller
Application Information
3946
Data Sheet
29319.150
Bootstrap Capacitor Selection. C
must be cor-
BOOT
rectly selected to ensure proper operation of the device. If
too large, time is wasted charging the capacitor, with the
result being a limit on the maximum duty cycle and PWM
frequency. If the capacitor is too small, the voltage drop can
be too large at the time the charge is trans ferred from the
C
to the MOSFET gate.
BOOT
To keep the voltage drop small:
Q
BOOT
>> Q
GATE
where a factor in the range of 10 to 20 is reasonable. Using
20 as the factor:
Q
BOOT
= C
BOOT
× V
BOOT
= Q
GATE
× 20
and
C
BOOT
= Q
GATE
× 20 / V
BOOT
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by:
Delta_v = Q
For example, given a gate charge, Q
GATE
/ C
BOOT
, of 160 nC, and the
GATE
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, C
, can be determined by:
BOOT
C
= (160 nC × 20) / 12 V 0.266 µF
BOOT
Therefore, a 0.22 µF ceramic (X7R) capacitor can be chosen
for the Boot capacitor.
At power-up and when the drivers have been disabled for
a long time, the bootstrap capacitor can be completely
discharged. In this case, Delta_v can be considered to be the
full high-side drive voltage, 12 V. Otherwise, Delta_v is the
amount of voltage dropped during the charge transfer, which
should be 400 mV or less. The capacitor is charged whenever
the S pin is pulled low, via a GL PWM cycle, and current
fl ows from VREG through the internal bootstrap diode
circuit to C
BOOT
.
Power Dissipation. For high ambient temperature
applications, there may be little margin for on-chip power
con sump tion. Careful attention should be paid to ensure that
the op er at ing conditions allow the A3946 to remain in a safe
range of junction temperature.
The power consumed by the A3946 can be es ti mat ed as:
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
where:
Pd_bias = VBB × I
, typically 3 mA,
VBB
and
Pd_cpump = (2V
Pd_cpump = (V
BB
BB
– V
– V
REG
REG
) I
) I
AV E
AV E
, for V
< 15 V, or
BB
, for VBB > 15 V,
in either case, where
In that case, the voltage drop on the BOOT pin, when the
high-side MOSFET is turned on, is:
Delta_v = 160 nC / 0.22 µF = 0.73 V
Bootstrap Charging. It is good practice to ensure that the
high-side bootstrap capacitor is completely charged before a
high-side PWM cycle is re quest ed.
The time required to charge the capacitor can be ap prox i mat ed by:
t
= C
CHARGE
(Delta_v / 100 mA)
BOOT
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
I
AV E
= Q
GATE
× 2 × f
and
Pd_switching_loss = Q
where
Ratio = 10 / (R
GATE
GATE
PWM
× V
REG
+ 10 ).
× 2 × f
PWM
Ratio,
7
Half
-Bridge Power MOSFET Controller
Application Block Diagrams
C1
C2
10 µF
P
0.47 µF
CP1CP2
+VBAT
3946
Data Sheet
29319.150
IN
Brake
VREF
L
Forward
External
+5 V
10
kΩ
R
DEAD
15.8 kΩ
L
IN
VREF
0.1 uF
~FAULT
DT
IN1
IN2
RESET
VREG
C
REG
10 µF
P
BOOT
C
BOOT
0.47 µF
IRF2807
R
GATE
GH
33 Ω
200
kΩ
S
IRF2807
R
GL
GATE
33 Ω
PGND
LGND
L
PL
P
DC
M
Motor
P
Control
Logic
Charge
Pump
Charge
Pump
Bootstrap
UVLO
I
LIM
High Side
Driver
Low Side
Driver
P
VREG
+5 Vref
L
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
L
Turn-On
Delay
L
L
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. T
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
= 1 µs; Q
DEAD
= 160 nC.
TOTAL
8
Data Sheet
29319.150
3946
Half
C2
10 µF
P
-Bridge Power MOSFET Controller
+VBAT
C1
0.47 µF
CP1CP2
VREF
Forward
Forward
10
kΩ
DC Motor #1
Slow
Decay
DC Motor #2
Slow
Decay
External
+5 V
L
VREF
VREF
0.1 uF
~FAULT
DT
IN1
IN2
RESET
VREG
P
C
REG
10 µF
P
BOOT
C
BOOT
0.47 µF
IRF2807
R
GATE
GH
33 Ω
200
kΩ
S
GL
PGND
LGND
L
L
DC Motor #1
DC Motor #2
R
GATE
33 Ω
M
P
IRF2807
200
kΩ
M
P
Control
Logic
Charge
Pump
Charge
Pump
Bootstrap
UVLO
I
LIM
High Side
Driver
Low Side
Driver
P
VREG
+5 Vref
L
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
L
Turn-On
Delay
L
L
Diagram B. Independent drivers. One high-side drive and one low-side drive.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
9
Data Sheet
29319.150
3946
Half
C2
10 µF
P
-Bridge Power MOSFET Controller
C1
0.47 µF
P
CP1CP2
+VBAT
VREF
Forward
Forward
10
kΩ
DC Motor #1
Slow
Decay
DC Motor #2
Slow
Decay
External
+5 V
L
VREF
VREF
0.1 uF
~FAULT
DT
IN1
IN2
RESET
VREG
C
REG
10 µF
P
DC Motor
#1
IRF2807
200
kΩ
M
200
kΩ
BOOT
R
GATE
GH
33 Ω
S
P
GL
PGND
LGND
L
R
33 Ω
GATE
PL
DC Motor
#2
IRF2807
M
P
Control
Logic
Charge
Pump
Charge
Pump
Bootstrap
UVLO
I
LIM
High Side
Driver
Low Side
Driver
P
VREG
+5 Vref
L
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
L
Turn-On
Delay
L
L
Diagram C. Independent drivers. Two low-side drives.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
Data Sheet
29319.150
3946
Half
C2
10 µF
P
-Bridge Power MOSFET Controller
+VBAT
C1
0.47 µF
CP1CP2
VREF
VREF
Forward
Reverse
CAUTION: ShootThrough Possible
External
10
kΩ
+5 V
L
VREF
0.1 uF
~FAULT
DT
IN1
IN2
RESET
VREG
C
REG
10 µF
P
BOOT
C
BOOT
0.47 µF
IRF2807
R
GATE
GH
33 Ω
200
kΩ
S
IRF2807
R
GL
GATE
33 Ω
PGND
LGND
L
PL
P
DC
M
Motor
P
Control
Logic
Charge
Pump
Charge
Pump
Bootstrap
UVLO
I
LIM
High Side
Driver
Low Side
Driver
P
VREG
+5 Vref
L
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
L
Turn-On
Delay
L
L
Diagram D. Dependent drivers with independent controls. Unidirectional, motor control with brake/coast,
but without dead time control.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
11
Half
3946
-Bridge Power MOSFET Controller
Data Sheet
29319.150
Pin Name Pin Description
VREG Gate drive supply. 1 1
CP2
CP1
PGND* External ground. Internally connected to the power ground. 4 4
GL
S
GH
BOOT
~FAULT Diagnostic output, open drain. Low during a fault condition. 9 9
Charge pump capacitor, positive side. When not using the charge
pump, leave this pin open.
Charge pump capacitor, negative side. When not using the charge
pump, leave this pin open.
Low-side gate drive output for external MOSFET driver. External
series gate resistor can be used to control slew rate seen at the
power driver gate, thereby controlling the di/dt and dv/dt of the S
pin output.
Directly connected to the load terminal. The pin is also connected
to the negative side of the bootstrap capacitor and negative supply
connection for the fl oating high-side drive.
High-side gate drive output for N-channel MOSFET driver. External
series gate resistor can be used to control slew rate seen at the
power driver gate, thereby controlling the di/dt and dv/dt of the S
pin output.
High-side connection for bootstrap capacitor, positive supply for the
high-side gate drive.
SOIC-16
(A3946KLB)
22
33
55
66
77
88
TSSOP-16
(A3946KLP)
IN1 Logic control. 10 10
IN2 Logic control. 11 11
RESET
LGND* External ground. Internally connected to the logic ground. 13 13
DT
VREF 5 V internal reference decoupling terminal. 15 15
VBB Supply Input. 16 16
*In the LB package, the PGND pin (4) and LGND pin (13) grounds are internally connected by the leadframe. In the LP package, however,
the PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
In the LP package, the exposed thermal pad is not connected to any pin, but should be externally connected to ground, to reduce noise
pickup by the pad.
Logic control input. When RESET = 0, the chip is in a very low
power sleep mode.
Dead Time. Connecting a resistor to GND sets the turn-on delay
to prevent shoot-through. Forcing this input high disables the dead
time circuit and changes the logic truth table.
12 12
14 14
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
Half
-Bridge Power MOSFET Controller
A3946KLB SOIC
.406
10.31
.398
10.11
16
.299
7.59
.291
7.39
.414
10.52
.398
10.11
21
.020
0.51
.014
.026
REF
0.36
0.66
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
.050
BSC
1.27
.012
.004
Webbed lead frame. Leads 4 and 13 are joined together within the device package.
.104
.096
0.30
0.10
2.64
2.44
8º
0º
.011
0.28
.009
0.23
.040
1.02
.020
0.51
3946
Data Sheet
29319.150
A3946KLP TSSOP with Exposed Thermal Pad
5.1
0.201
4.9
0.193
16
16
4.5
0.177
4.3
6.6
6.2
0.260
0.244
.30
.19
0.169
21
21
0.012
0.007
Dimensions in millimeters
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
U.S. Customary dimensions (in.) in brackets, for reference only
A
A
Exposed thermal pad (bottom surface)
Exposed thermal pad (bottom surface)
3
3
BSC
BSC
A
A
0.118
0.118
.65
.65
BSC
BSC
.026
.026
3
0.118
3
0.118
BSC
BSC
.75
0.030
.45
0.018
1.20
MAX
.15
0.006
.00
0.000
NOTES:
1. Exact body and lead confi guration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel.
0.047
8º
0º
0.20
0.09
1
0.039
REF
.25
0.010
.25
0.010
BSC
BSC
Seating Plane
Seating Plane
Gauge Plane
Gauge Plane
0.008
0.004
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
13
Half
3946
-Bridge Power MOSFET Controller
Data Sheet
29319.150
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such de par tures from the detail spec i fi ca tions as may be
required to permit improvements in the per for mance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written
approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights
of third parties which may result from its use.
Copyright©2003, 2004 AllegroMicrosystems, Inc.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
14
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