ALLEGRO 3946 User Manual

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3946

Half-Bridge Power MOSFET Controller

Data Sheet

29319.150

A3946KLB SOIC

VREG

Scale 1:1

CP2

CP1

PGND

GH

BOOT

1

2

3

4

GL

5

S

6

7

8

16

15

14

13

12

11

10

9

VBB

VREF

DT

LGND

RESET

IN2

IN1

~FAULT

A3946KLP TSSOP with Exposed Thermal Pad

Scale 1:1

VREG

CP2

CP1

PGND

GH

BOOT

1

2

3

4

GL

5

S

6

7

8

16

15

14

13

12

11

10

9

VBB

VREF

DT

LGND

RESET

IN2

IN1

~FAULT

AB SO LUTE MAX I MUM RAT INGS

Load Supply Voltage, VBB............................. 60 V

Logic Inputs ..................................–0.3 V to 6.5 V

Pin S……..........................................–4 V to 60 V

Pin GH ...........................................–4 V to 75 V

Pin BOOT….. ................................–0.6 V to 75 V

Pin DT ........................................................ V

Pin VREG ......................................–0.6 V to 15 V

Package Thermal Resistance, R

JA

A3946KLB..................................... 48°C/W

A3946KLB..................................... 38°C/W

A3946KLP ..................................... 44°C/W

A3946KLP ..................................... 34°C/W

Operating Temperature Range, TA.. –40°C to +135°C
Junction Temperature, T
Storage Temperature Range, T

Notes:

1. Measured on a two-sided PCB with 3 in.
2 oz. copper.

2. Measured on JEDEC standard High-K board.

...........................+150°C

J

....-55°C to +150°C

S

2

REF

of

1

2

1

2

The A3946 is designed specifi cally for ap pli ca tions that require
high power unidirectional dc motors, three-phase brushless dc motors, or
other inductive loads. The A3946 provides two high-current gate drive
outputs that are capable of driving a wide range of power N-channel

MOSFETs. The high-side gate driver switches an N-channel MOSFET

that controls current to the load, while the low-side gate driver switches
an N-channel MOSFET as a synchronous rectifi er.

A bootstrap capacitor provides the above-battery supply voltage
required for N-channel MOSFETs. An internal charge pump for the
high side allows for dc (100% duty cycle) operation of the half-bridge.

The A3946 is available in a choice of two power pack ag es: a
16-lead

SOIC with copper batwing power tab (part number suffi x LB),

and a 16-lead TSSOP with ex posed thermal pad (suffi x LP).

FEATURES

 On-chip charge pump for 7 V minimum input supply voltage
 High-current gate drive for driving a wide range of

N-channel

MOSFETs

 Bootstrapped gate drive with charge pump for 100% duty cycle
 Overtemperature protection
 Undervoltage protection
 –40ºC to 135ºC ambient operation

Always order by complete part number:

Part Number Package

A3946KLB
A3946KLP

16-Lead SOIC; Copper Batwing Power Tab
16-Lead TSSOP; Exposed Thermal Pad

Half

-Bridge Power MOSFET Controller

Functional Block Diagram

+VBAT

3946

Data Sheet

29319.150

L

10

kΩ

VREF

R

DEAD

L

VREF

0.1 uF
X7R
10 V

~FAULT

DT

IN1

IN2

RESET

C2

0.47 uF, X7R
V rated to VBAT

P

+5 Vref

L

L

L

VBB

L

Protection
VREG Undervoltage
Overtemperature
UVLOBOOT

Turn-On

Delay

P

Control

Logic

C1

0.47 uF, X7R
V rated to VBAT

Charge

Pump

Charge

Pump

Bootstrap

UVLO

CP1CP2

VREG

C

REG

I

LIM

High Side

Driver

Low Side

Driver

P

BOOT

GH

S

VREG

GL

PGND

LGND

L

P

C

BOOT

R

GATE

P

R

GATE

PL

Control Logic Table

IN1 IN2 DT Pin RESET GH GL Function

X X X 0 Z Z Sleep mode

00R

01R

10R

11R

- LGND 1 L H Low-side FET ON following dead time

DEAD

- LGND 1 L L All OFF

DEAD

- LGND 1 L L All OFF

DEAD

- LGND 1 H L High-side FET ON following dead time

DEAD

0 0 VREF 1 L L All OFF

0 1 VREF 1 L H Low-side FET ON

1 0 VREF 1 H L High-side FET ON

1 1 VREF 1 H H CAUTION: High-side and low-side FETs ON

www.allegromicro.com

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

2

Half

3946

-Bridge Power MOSFET Controller

Data Sheet

29319.150

ELECTRICAL CHARACTERISTICS at T

= –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)

A

Characteristics Symbol Test Conditions

VBB Quiescent Current I

VREG Output Voltage V

Charge Pump Frequency F

VREF Output Voltage V

VBB

REG

REF

RESET = High, Outputs Low

RESET = Low

V

> 7.75 V, I

BB

V

= 7 V to 7.75 V, I

BB

CP1, CP2

CP

I

≤ 4 mA, C

REF

= 0 mA to 15 mA 12.0 13 13.5 V

reg

= 0.1 µF 4.5

REF

Gate Output Drive

Turn On Time t

Turn Off Time t

Pullup On Resistance R

Pulldown On Resistance R

Short Circuit Current –
Source

Short Circuit Current –
Sink

GH Output Voltage V

GL Output Voltage V

DSDOWN

rise

fall

DSUP

–

–

C

= 3300 pF, 20% to 80%

LOAD

C

= 3300 pF, 80% to 20%

LOAD

Tj = 25°C

= 135°C

T

j

Tj = 25°C

= 135°C

T

j

tpw < 10 µs 800

tpw < 10 µs 1000

tpw < 10 µs, Bootstrap Capacitor fully charged V

GH

GL

Timing

R

Dead Time (Delay from

Turn Off to Turn On)

Propagation Delay t

t

DEAD

PD

= 5 kΩ 200 350 500 ns

dead

R

= 100 kΩ 567µs

dead

Logic input to unloaded GH, GL. DT = VREF

= 0 mA to 15 mA 11.0

reg

–

V

Limits

Min. Typ. Max. Units

–

––

–

–

–

–

–

–

–

– 1.5

REG

– 0.2

REG

––

36mA

10 µA

–

62.5

–

60 100 ns

40 80 ns

4

6

2

3

––

––

13.5 V

–

5.5 V

kHz

–

–

–

–

mA

mA

––

––

150 ns

Ω

Ω

Ω

Ω

V

V

www.allegromicro.com

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

3

Half

3946

-Bridge Power MOSFET Controller

Data Sheet

29319.150

ELECTRICAL CHARACTERISTICS at T

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Protection

VREG Undervoltage V

VREG Undervoltage V

BOOT Undervoltage V

BOOT Undervoltage V

Thermal Shutdown Temperature T

Thermal Shutdown Hysteresis ∆T

REGON

REGOFF

BSOFF

Logic

Input Current I

I

Logic Input Voltage V

V

Logic Input Hysteresis

Fault Output

V

BSON

JTSD

IN(1)

IN(0)

IN(1)

IN(0)

–

V

ol

oh

V

REG

V

REG

V

BOOT

V

BOOT

Temperature increasing

Recovery = T

J

IN1 VIN / IN2 VIN = 2.0 V

IN1 VIN / IN2 VIN = 0.8 V

RESET pin only

IN1 / IN2 logic high 2.0

RESET logic high 2.2

Logic low

All digital inputs 100

I = 1 mA, fault asserted

V = 5 V

= –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)

A

Limits

increasing 8.6 9.1 9.6 V

decreasing 7.8 8.3 8.8 V

increasing 8 8.75 9.5 V

decreasing 7.25 8.0 8.75 V

170

15

40 100 µA

16 40 µA

–

–

1 µA

JTSD

– ∆T

–

J

–

–

–

––

––

––

––

–

––

––

0.8 V

300 mV

400 mV

1 µA

°C

°C

V

V

www.allegromicro.com

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

4

Half

-Bridge Power MOSFET Controller

Functional Description

3946

Data Sheet

29319.150

VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side
gate drive.

The VREG capacitor, C

, must supply the instantaneous

REG

current to the gate of the low-side MOSFET. A 10 µF, 25 V
capacitor should be adequate. This capacitor can be either
electrolytic or ceramic (X7R).

Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line
is high and any of the following conditions are present:

• Undervoltage conditions on VREG (UVREG) or on the
internal logic supply VREF (UVREF). These conditions
set a latched fault.

• A junction temperature > 170°C (OVERTEMP). This con­dition sets a latched fault.

• An undervoltage on the stored charge of the BOOT capaci­tor (UVBOOT). This condition does NOT set a latched
fault.

An overtemperature event signals a latched fault, but does
not disable any output drivers, regulators, or logic inputs.
The user must turn off the A3946 (e.g., force the RESET line
low) to prevent damage.

cleared immediately, and remains cleared. If the power is
restored (no UVREG or UVREF), and if no OVERTEMP
fault exists, then the latched fault remains cleared when the
RESET line returns to high. However, FAULT = 1 may still
occur because a UVBOOT fault condition may still exist.

Charge Pump. The A3946 is designed to ac com mo date
a wide range of power supply voltages. The charge pump
output, VREG, is regulated to 13 V nominal.

In all modes, this regulator is current-limited. When V

BB

< 8 V, the charge pump operates as a voltage doubler. When
8 V < VBB< 15 V, the charge pump operates as a voltage
doubler/PWM, current-controlled, voltage regulator. When
VBB>15 V, the charge pump operates as a PWM, current-con­trolled, voltage regulator. Effi ciency shifts, from 80% at VBB=
7 V, to 20% at VBB = 50 V.

CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
confi guration is NOT recommended. There is no assurance
that one of the regulators will not dominate, taking on all of
the load and back-biasing the other regulators. (For example,
this could occur if a particular regulator has an internal refer­ence voltage that is higher that those of the other regulators,
which would force it to regulate at the highest voltage.)

The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.

Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create
a UVBOOT fault condition, which in turn inhibits the high­side driver and creates a FAULT = 1. This fault is NOT
latched. To remove this fault, momentarily turn on GL to
charge the BOOT capacitor.

Latched faults may be cleared by a low pulse, 1 to 10 µs
wide, on the RESET line. Throughout that pulse (despite
a possible UVBOOT), FAULT = 0; also the fault latch is

www.allegromicro.com

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is
high), the gate drive outputs stay disabled and a fault remains
asserted until VREF and VREG pass their undervoltage
thresholds. When powering up, before starting the fi rst boot-
strap charge cycle, wait until t = C

⁄ 4 (where C

REG

REG

is in

µF, and t is in ns) to allow the charge pump to stabilize.

When powered-up (not in Sleep Mode), if the RESET line
is low for > 10 µs, the A3946 may start to enter Sleep Mode
(V

< 4 V). In that case, ~FAULT = 1 as long as the RESET

REF

line remains low.

If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.

5