ALLEGRO 3936 User Manual

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3936
DMOS THREE-PHAS
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB........................... 50 V
Output Current, I
Logic Supply Voltage, VDD......................... 7.0 V
Logic Input Voltage Range, VIN
(tW>30 ns) .......... -0.3 V to V
(tW<30 ns) ................ -1.0V to VDD +1V
Sense Voltage, V Reference Voltage, V Package Power Dissipation, P Operating Temperature Range, T
Junction Temperature, TJ......................... +150°C
Storage Temperature Range, T
* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
D
A
S
................................... ±3 A*
OUT
+ 0.3 V
DD
................................. 0.5 V
SENSE
................................ VDD
REF
............................................... 3.9 W
................................ -20°C to +85°C
............................... -55°C to +150°C
PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of three­phase brushless dc motors, the A3936SED is capable of peak output currents to ± 3 A and operating voltages to 50 V. Internal fixed off-time PWM current­control timing circuitry can be configured to operate in slow-, fast- and mixed­decay modes.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with hysteresis, and crossover current protection. Special power up sequencing is not required.
The A3936 is supplied in a 44-pin plastic PLCC with a copper batwing tabs (suffix ‘ED’). The power tabs are at ground potential and need no electrical isolation. This device is also available in a lead-free version (100% matte tin leadframe).
Features
±3 A, 50 V Continuous Output Rating Low Configurable Mixed, Fast and Slow Current-Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Tachometer Output for External Speed Control Loop
Always order by complete part number Part Number Package A3936SED 44-pin PLCC A3936SED-T 44-pin PLCC, Lead-free
r
Outputs (typically 500 m source, 315 m sink)
DS(on)
A3936-DS Rev. 1
3936 Three Phase PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
.22uf/100V
.22uf/50V
VREG
V
DD
REGULATOR CHARGE PUMP
CP2
CP1
VCP
HALL
HALL
HALL
TACH
HBIAS
HA+
HB+
HC+
SLEEP
DIR
EXTMODE
BRAKE
ENABLE
HA-
HB-
HC-
SR
Comm
Logic
Control
Logic
BANDGAP
GATE
DRIVE
OVERVOLTAGE
UNDERVOLTAGE
AND FAULT
DETECT
VCPVREG
ZERO
DETECT
+-
CURRENT
VBB1
VBB2
OUTA
OUTB
OUTC
LSS2
LSS1
SENSE
R
GND
.22uf/50V
.1uF
S
VDD
BLANK
OSC
PFD1 PFD2
PWM
TIMER
+-
SENSE
CURRENT
BUFFER/ DIVIDER
REF
3936 Three Phase PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TJ= +25°C, VBB = 50 V, VDD=5.0V,f
< 50KHz (unless noted otherwise)
PWM
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load SupplyVoltage Range VBB Operating 9 50 V
During Sleep Mode 0 50 V
Output Leakage Current I
Output On Resistance R
BodyDiodeForward Voltage V
Motor Supply Current I
Logic Supply Current
DSS
DSON
F
BB
I
DD
V
OUT=VBB
V
= 0 V <–1.0 -20 µA
OUT
SourceDriver, I Sink Driver, I
= -3A .55
OUT
=3A .35
OUT
–<1.020 µA
Source Diode, IF= -3A 1.4 V Sink Diode, IF=3A 1.3 V f
<50kHz 4 7 mA
PWM
Charge Pump On, Outputs Disabled 2 5 mA Sleep Mode 20 uA f
<50kHz 10 mA
PWM
Control Logic
Logic Supply Voltage Range V Logic Input Voltage V
Logic Input Current I (except ENABLE) I Logic Input Current I ENABLE Input I
Outputs Off 8 mA Sleep Mode (Inputs belo w.5V) 100 µA
DD
IN(1)
V
IN(0)
IN(1)
IN(0)
IN(1)
IN(0)
OSC
Operating 3 5.0 5.5 V
VDD*.5 V
––V
*.2 V
DD
VIN=VDD*.5 -20 <1.0 20 µA VIN=VDD*.2 -20 <-1.0 20 µA VIN=VDD*.5 100 µA VIN=VDD*.2 30 µA OSC shorted to GND 3 4 5 MHzInternalOscillator f R
= 51K 3.4 4 4.6 MHz
OSC
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