Alinco DJ-438, DJ-496, DJ-493 Service Manual
DJ-493
DJ-496/438
Servic e Man ua l
CONTENTS
SPECIFICATIONS
1) G E NE R AL.............................................................................2
2) TRANSM ITTER...................................................................2
3) RECE IVER............................................................................2
CIRCUIT DESCRIPTION
1) Receiver Sy s tem ............................................................3, 4
2) Transmitter S ystem.............................................................4
3) PLL Synthesizer Circuit
4) CPU and Peripheral C ircuits
5) M 38267M8L252GP (X A 0725)..................................... 6 - 8
SEMICONDUCTOR DATA
1) NMJ2070M T 1 (XA0210) ..................................................9
2) AT24C16N-10SI-2.7TER (X A 0368)................................9
3) M 5222FP-600C (XA0385)
4) TK14521MTL (X A 0515).................................................. 11
5) M64076AGP (XA0352)
6 ) NJM2904V-TE1 (XA0573) ............................................. 12
7) NJM2902V-TE1 (XA0596) ............................................. 12
8 ) S-81350HG-KD-T1 (XA0724) ....................................... 13
9) S-80845ALM P-EA9-T2 (XA0620) ................................ 13
10) 2SK2975 (XE00 38)........................................................... 13
11) Transistor, Diode, and LED Ontline Drawings
12) LCD Connection (EL0044)............................................ 14
...............................................
......................................
.............................................
................................................... 12
4, 5
5, 6
...........
10
14
EXPLODED VIEW
1) Front V iew............................................................................15
2) R earVie w ............................................................................16
PARTS LIST (DJ-493)
MAIN U nit
Mechanical P a rts..............................................................22
Packing P arts......................................................................22
PARTS LIST (DJ-496)
MAIN U n it.....................................................................23-27
Mechanical Pa rts...............................................................28
Packing P arts......................................................................28
ADJUSTMENT
1) Required Test E quipm ent
2) Adjustment M ode
PC BOARD VIEW
MAIN U n it.....................................................................35, 36
SCHEMATIC DIAGRAM
BLOCK DIAGRAM
.................................................................... 17-21
........................................
.......................................................31-34
.............................................
........................................................
29, 30
37, 38
39, 40
SNCO, inc.
SPECIFICATIONS
1) GENERAL
Frequency coverage
Mode
Channel steps
Memory channels
Antenna connector
Frequency stability
Microphone input impedance
Power supply requirement
Current drain (at 13.8 V DC)
Usable temperature range
Dimensions
(Projections not included)
Weight
DTMF (DJ-496)
Sub audible Tone(CTCSS)
Sub audible Tone (DCS)
DJ-493T
DJ-496T
DJ-438TA2
F3E (FM)
5,10,12.5,15,20,25, & 30kHz
40channels+1 CALL channel
BNC (50Q unbalanced)
±5 ppm
2kfi nominal
7.0 - 16.0V DC (negative ground)
1.4A (typical) Transmit high at 5W
200mA (typical) Receive at 280mW
50mA (typical) standby
20mA (typical) Battery save on
-10 ~ +60°C (14 ~ 140°F)
56 (W) x 124 (H) x 40 (D) mm (with EBP-48N)
2.2"(W) x 4.88"(H) x 1,57"(D) inches (with EBP-48N)
Approx. 375g (13.2oz) (with EBP-48N)
16 Buttons Keypad
encoder/decoder installed (39tones)
encoder/decoder installed (104codes)
TX 430 ~ 449.995MHz RX 430 ~ 449.995MHz
E
TX 430 - 439.995MHz RX 430 ~ 439.995MHz
TA2
TX 450 ~ 469.995MHz RX 450 ~ 469.995MHz
TX 430 ~ 449.995MHz RX 430 ~ 449.995MHz
E
TX 430 ~ 439.995MHz RX 430 ~ 439.995MHz
TX 450 ~ 469.995MHz RX 450 ~ 469.995MHz
2) TRANSMITTER
Output power
Modulation system
Spurious emissions
Max. frequency deviation
3) RECEIVER
Receive system
Intermediate frequencies
Sensitivity(12dB SINAD)
Selectivity
Audio output power
2
Approx. 4W EBP-48N installed
Approx. 5W 13.8V DC
Approx. 0.8W (LOW)
Variable reactance frequency modulation
Less than -60dB
±5 kHz
Double conversion superheterodyne
1st 45.1 MHz/2nd 455kHz
Less than -12.0dB|x (0.25V)
-6dB :12kHz or more
-60dB : 26kHz or less
280mW (typical with an 8Q load)
200mW (8i3 10% THD)
CIRCUIT DESCRIPTION
1) Receiver System
The receiver system is a double superheterodyne system with a 45.1 MHz first IF and a 455kHz second IF.
1. Front End
The received signal at any frequency in the 430.00- to 449.995-MHz range is
passed through the low-pass filter (L2, L3, L8, C2, C9, C10, C11, and C62)
and high-pass filter (C56, C57, C61, L25 and D25), and amplified by the RF
amplifier (Q9). The signal from Q9 is then passed through the tuning circuit
(L19, L20, L21 and varicaps D12, D13 and D14) and converted into 45.1MHz
by the mixer (Q10). The tuning circuit, which consists of L25, L19, L20, L21,
D15, D12, D13 and D14 is controlled by the tracking voltage form the CPU so
that it is optimized for the reception frequency. The local signal from the VCO
is passed through the buffer (Q11), and supplied to the source of the mixer
(Q10). The radio uses the lower side of the superheterodyne system.
2. IF Circuit
The mixer mixes the received signal with the local signal to obtain the sum of
and difference between them. The crystal filter (XF1) selects 45.1MHz fre
quency from the results and eliminates the signals of the unwanted frequen
cies. The first IF amplifier (Q8) then amplifies the signal of the selected fre
quency.
3. Demodulator Circuit
4. Audio Circuit
After the signal is amplified by the first IF amplifier (Q8), it is input to pin 16 of
the demodulator IC (IC4). The second local signal of 45.555MHz, which is
oscillated by the internal oscillation circuit in IC4 and crystal (X2). Then, these
two signals are mixed by the internal mixer in IC4 and the result is converted
into the second IF signal with a frequency of 455kHz. The second IF signal is
output from pin 3 of IC4 to the ceramic filter (FL1), where the unwanted fre
quency band of that signal is eliminated, and the resulting signal is sent back
to the IC4 through pin 5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC4, and output as an audio signal
through pin 10.
The audio signal from pin 10 of IC4 is compensated to the audio frequency
characteristics in the de-emphasis circuit (R106, R107, C128, C127) and am
plified by the AF amplifier (Q27). The signal is then input to pin 2 of the elec
tronic volume (IC6) for volume adjustment, and output from pin 1. The ad
justed signal is sent to the audio power amplifier (IC5) through pin 2 to drive
the speaker.
3
5. Squelch Circuit
2) Transmitter System
1. Modulator Circuit
2. Power Amplifier Circuit
The signal except for the noise component in AF signal of 104 is cut by the
active filter inside 1C. The noise component is amplified and rectified, then
converted to the DC voltage to output from pin13 of IC4. The voltage is led to
pin 2 of CPU and compared with the setting voltage. The squelch will open if
the input voltage is lower than the setting voltage.
The audio signal is converted to an electric signal in either the internal or
external microphone, and input to the microphone amplifier (IC8). IC8 con
sists of two operational amplifiers; one amplifier (pins 5, 6, and 7) is composed
of pre-emphasis and IDC circuits and the other (pins 1, 2, and 3) is composed
of a splatter filter. The maximum frequency deviation is obtained by VR1 and
input to the cathode of the varicap of the VCO, to change the electric capacity
in the oscillation circuit. This produces the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the pre-drive IC
(IC1) and drive amplifier (04), and input to the final amplifier (02). The signal
is then amplified by the final amplifier (02) and led to the antenna switch (D2)
and low-pass filter (L5, L3,12, C24, C11, 010, and C9), where unwanted high
harmonic waves are reduced as needed, and the resulting signal is supplied
to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by D7, con
verted to DC, and then amplified by a differential amplifier. The output voltage
controls the bias voitage from the source of 02 and 04 to maintain the trans
mission power constant.
3) PLL Synthesizer Circuit
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC9) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC2). The oscillated signal from the
VCO is amplified by the buffer (05, 037) and input to pin 6 of IC2. Each
programmable divider in IC2 divides the frequency of the input signal by N
according to the frequency data, to generate a comparison frequency of 5 or
6.25kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by di
viding the 21,25MHz reference oscillation (X1) by 4250 or 3400, according to
the data from the CPU (IC9). When the resulting frequency is 5kHz, channel
steps of 5, 10, 15, 20, 25, 30, and 50kHz are used. When it is 6.25kHz, the
4 12.5kHz channel step is used.
3. Phase Comparator Circuit
The PLL (IC2) uses the reference frequency, 5 or 6.25kHz. The phase com
parator in the IC2 compares the phase of the frequency from the VCO with
that of the comparison frequency, 5 or 6.25kHz, which is obtained by the inter
nal divider in IC2.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference
frequency and VCO output frequency, the charge pump output (pin 8) of IC2
generates a pulse signal, which is converted to DC voltage by the PLL loop
filter and input to the varicap of the VCO unit for oscillation frequency control.
5. VCO Circuit
A Colpitts oscillation circuit driven by Q3 directly oscillates the desired fre
quency. The frequency control voltage determined in the CPU (IC9) and PLL
circuit is input to the varicaps (D3). This change the oscillation frequency, which
is amplified by the VCO buffer (Q5) and output from the VCO unit.
4) CPU and Peripheral Circuits
1. LCD Display Circuit
The CPU turns ON the LCD via segment and common terminals with 1/4 the
duty and 1/4 the bias, at the frame frequency is 112.5Hz.
2. Display Lamp Circuit
When the LAMP key is pressed, “H” is output form pin 42 of CPU (IC9) to the
bases of Q19, Q24 and Q25.
3. Reset and Backup
When the power form the DC jack or external battery increases from Circuits 0
V to 2.5V or more, “H” level reset signal is output from the reset IC (IC11) to pin
33 of the CPU (IC9), causing the CPU to reset. The reset signal, however,
waits at 100, and does not enter the CPU until the CPU clock (X3) has stabi
lized.
4. S(Signal) Meter Circuit
The DC potential of pin 8 of iC4 is input to pin 1 of the CPU (IC9), converted
from an analog to a digital signal, and displayed as the S-meter signal on the
LCD.
5. DTMF Encoder (DJ-496)
The CPU (IC9) is equipped with an internal DTMF encoder. The DTMF signal
is output from pin 10, through R179 and R180 (for level adjust-ment), and then
through the microphone amplifier (IC8), and is sent to the varicap of the VCO
for modulation. At the same time, the monitor-ing tone passes through the AF
circuit and is output form the speaker.
6. CTCSS Encoder
7. DCS Encoder
8. CTCSS, DCS Decoder
9. Clock Shift
The CPU (IC9) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of the CPU to the varicap (D4) of the
The CPU (IC9) is equipped with an internal DCS code encoder. The code (023
to 754) is output from pin 9 of the CPU to the varicap (D16) of the PLL refer
ence oscillator. When DCS is ON, DCS MUTE circuit (Q12-ON, Q18-ON, 015-
OFF) works. The modulation activates in X1 side only.
The voice band of the AF output signal from pin 10 of IC4 is cut by sharp active
filter IC7 (VCVS) and amplified, then led to pin 4 of CPU. The input signal is
compared with the programmed tone frequency code in the CPU. The squelch
will open when they match.
In the unlikely event that CPU clock noise is present on a particular operating
frequency programmed into the radio, you can shift the CPU clock frequency
to avoid the CPU clock-noise. The output signal from pin 31 of the CPU turns
on Q35. Then the oscillation frequency of X3 will be shifted about 300 ppm.
5) M38267M8L252GP (XA0725)
CPU
Terminal Connection
(TOP VIEW)
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SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1 @7
SEGO
VREF
AVSS
COM3
COM2
COMI
COMO
-----
--
-----
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-
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VL3
--
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VL2
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C2
C1
-----
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VL1
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• P14/SEG38
• P15/SEG39
• P16
• p i ;
P20
• P21
- P22
- P23
- P24
• P25
• P26
• P27
VSS
- XOUT
XIN
• XCOUT
XCIN
RESET
P70/INTO
• P71
• P72
• P73
• P74
- P75
• P76
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No.
1
2
3 P65/AN5
4 P64/AN4
5 P63/SCLK22/AN3
Pin Name
Function I/O PU Logic Description
P67/AN7 SMT
P66/AN6 SQL I
BAT I
TIN I
BP1
6 P62/SCLK21/AN2 BP2 I
7
P61/SOUT2/AN1 DCSW o
8 P60/SIN2/ANO
9 P57/ADT/DA2
10
11
12
P56/DA1
P55/CNTR1
P54/CNTR0 TBST I/O
13 P53/RTP1
14
15
16
17
18
P52/RTP0 MUTE
P51/PWM3 CLK
P50/PWM0 DATA
P47/SROY1 TRESET
P46/SCLK1 STBP
19 P45/TXD
20
21
P44/RXD RTX I
P43/0/TOUT
22 P42I/NT2
23 P41/INT1
24
25
P40 SD
P77
26 P76
27
28
29
30
P75
P74
P73
P72 AFP
31 P71
32
P70/INTO BU I
33 RESET
34
35
Xcin
Xcout
36 Xin
37
Xout
38 v'ss
39
40
41
P27
P26
P25
F/M/KEY I
CTOUT 0
DTOUT o
SCL
BP4 I
UTX
BEEP
RE2
RE1 I
PTT I
BP6
P5C 0
TCO
1 v^V-/
R5C o
CLSFT o
RESET I
Xcin
Xcout
Xin
Xout
GND
PSW I
SDA
C5C 0
42 P24 LAMP
43 P23
44
P22 KI1
45 P21
46 P20
47
P17
KI0
K!2
KI3
K03
48 P16 K02
49 P15/SEG39 KOI
50 P14/SEG38
KOO 0
51 P13/SEG37 H/L
52
P12/SEG36 DA2 0
53 P11/SEG35 DA1 0
54
55
P10/SEG34
P07/SEG33
DA0
d Y D
L .A I
-
I
-
-
-
-
I
-
-
-
-
-
-
0
*
- -
-
I/O
-
0
-
I/O
-
I/O
-
0
-
0
-
-
I/O
*
I
*
-
0
-
*
I
-
r\
-
-
-
0
-
-
-
- - - -
- - - -
- - -
- - -
- - -
-
-
0
-
-
0
A/D
A/D
A/D
A/D
A/D
A/D
Activ high
A/D
D/A
D/A
Pulse Serial clock for EEPROM
Pulse/Activ low
Activ high
Pulse Serial dock output for PLL,CTCSS
Pulse
Activ low/Pulse
Pulse
Pulse UART data transmission output
Pulse UART data reception output
Pulse/Activ low
Avtiv low
Avtiv low
Avtiv low
Activ high PTT input
Activ high
Activ low
a . i
____
AAUllV IUW
Activ low
Activ low
Activ high
Activ low
Activ low
Avtiv low
Pulse Serial data for EEPROM
Activ high C5V power ON/OFF output
Activ high
I * Avtiv low
*
I
!
I
0
0
0
0
0
Avtiv low
*
Avtiv low
*
Avtiv low
-
Avtiv low
-
Avtiv low
-
Avtiv low
-
Avtiv low
- -
- -
- -
- -
T“
-
S-meter input
Noise level input for squelch
Low battery detection input
CTGSS tone input/DSG code input
Band plan 1
Band plan 2
DCS signal mute
Function/Moniter key input
CTCSS tone output/DCS tone output/Tuning voltage out
DTMF output/EVR control output
Tone burst output
Band plan 4
Microphone mute
Serial data output lor PLLCTCSS, PLL unlock signal input
Trunking board detection (when PSW is on)/Trunking board reset
Strobe for PLL IC
Beep tone/Band plan 3(when PSW is on)
Rotary encoder input
Signal detection output
Band plan 6
PLL power ON/OFF output
TX power ON/OFF output
RX power ON/OFF output
AF AMP power ON/OFF output
CLOCK frequency shift
Backup signal detection input
Reset input
Main clock input
Main clock output
CPU GND
Power switch input
Lamp ON/OFF
Key matrix input
Key matrix output
Tx power H/L
DA converter for output power
DA converter for output power
DA converter for output power
UART line SW/External control port
7
No.
li e T
57 '
58 "
59 "
60
61
62 '
63
64 "
65 “
66 '
67 '
68 '
69 "
70 ‘
71
111
73 ~
74 "
75 ‘
-7/-'
( O
T T "
78 ~
79
80
81
82
83
84
85
86
87 '
88
89
90
91
92
93
~94~
95
96
97
98
99
100
Pin Name Function I/O PU Logic Description
P06/SEG32 AFC
P05/SEG31
P04/SEG30
P03/SEG29
P02/SEG28
P01/SEG27
P00/S EG26
P37/SEG25
P36/SEG24
P35/SEG23
P34/SEG22
P33/SEG21
P32/SEG20
P31/SEG19
P30/SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEGO
S31 O
S30 O
S29 O
S28
S27 O
S26 O
S25 O
S24 O
S23 O
S22 O
S21
S20
S19 O
S18 O
S17 O
S16 O
S15 O
S14 O
S13 O
S11 o
S10 o
S9 O
S8 O
S7 O
S6 O
S5 O
S4 O
S3 O
S2
S1 o
SO o
Vcc VDD
Vref
Avss
COM3
r n M Q
Vref AD converter power supply
Avss AD converter GND
COM3 O LCD COM3 output
nniwio
O Activ high AF tone control
O
O
LCD segment signal
O
CPU power terminal
n
LCD COM2 output
COM1 COM1 O LCD COM1 output
COMO COMO O LCD COMO output
VL3
VL2
VL3
VL2
LCD power supply
C2
C1
VL1
C1
VL1
A/D LCD power supply
SEMICONDUCTOR DATA
1) NMJ2070M T1 (XA0210)
Low Voltage Power Amplifier
Equivalent Circuit
Parameter
Supply voltage
Idle current
Output voltage
Input bias current
Output power
UldllM IIUI1
Voltage gain
Input impedance f=1kHz
Equivalent input noise
voltage
Power supply voltage
rejection ratio
Power gain band width
(- 3dB)
RL=
THD=10%, f= 1 kHz
THD=10%, f=1kHz V+=6V, RL=4
f-v_ r\ A\ki i a i 4 i-i i_
ru*u.^vY, n L ^ , i= i
f=1kHz
Rs=10k
f= 100Hz, Cx»100pF
RL=8 , Po=250mW
Condition
Symbol
V+
Vo
V+=6V, RL=4
V+-4.5V, RL-4
V+=3V, R L-4
V+=2V, RU 4
V+-4.5V , RL=4
A curve Vn1
B=22Hz to 22kHz
Po
Tnu
Av 41 44 47 dB
ZlN
Vn2
SVR
P.B
V+=6 V, Ta=25±2‘C
Min. Typ. Max.
1.8
lo
-
-
Ib
-
0.5 0.6
-
-
-
-
-
-
100
-
-
24 30
'
-
4 7 mA
2.7
200
0.32
120
30
500
250
0.25
- -
2.5
3
200
15
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
V
V
nA
W
W
mW
mW
mW
mW
%
k
MV
MV
dB
kHz
2) AT24C16N-10SI-2.7TER (XA0368)
16K bits CMOS Serial EEPROM
AO
A 1
A2
GND
Pin Name
A0 10 A2 Address inputs
SDA Serial Data
SCL Serial Clock
Test Test Input (GND or Vcc)
NC
No connection
Function
9
3) M5222FP-600C (XA0385)
Electronic Volume
VI1 I
VI2
O —
----
VW—(e>
fc -0
7 ^ - °
10
l=WHI
4) TK14521MTL (XA0515)
IF System
c
H
3
Q.
Û
z
0
w
m
O
co
O
Ta = 25°C, Vcc = 3V, fin = 10.7MHz, fm = 1kHz, Mod = ±3kHz
Parameter Symbol
Supply Current Icc 4.3 7.0
Mixer + IF part
Limiting Sensitivity
Output Voltage Vo
Distortion THD 0.8
S/N
AM Rejection Ratio
Mixer Coversion Gain Gm 20 26 32
Mixer 3rd Intercept point ICP -10 -3
Mixer Input Impedance Rim 2.8 3.6 4.4
Mixer Output Impedance
Limiter Input Impedance
RSSI part
RSSI Output Current 1 Irssi 1 41 60 88
RSSI Output Current 2
RSSI Output Current 3 Irssi 3 10 17 25
Squelch BPF part
Center Frequency 1 fCT 1 10.5 15.0 21.0
Center Frequency 2 fCT 2 21.0 30.0
Center Frequency 3 fCT 3 38.5 55.0
Squelch Output Current Iso 6 10
Squelch ON Voltage VSQ(ON) 0.40
Squelch OFF Voltage
ç
E
W
O
CO
O
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co
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x>
<
s
B
>
Limit
S/N 40 46 52 dB
AMRR 30 40 dB
Rom 1.2
Rifin 1.2
I RSSI 2 22 40 59
VSQ(OFF) 0.50 0.57
'O
<
o
Ratings
Min Typical
-94
200 300 400 mVrms
-100 -106
1.5 1.9
1.5 1.9
0.47
?
a
o
ra
Z)
E
0)
Max
2.8
39.0 kHz
71.5 kHz
0.54 V
0.64 V
o
«
E
E
0
Q
t
o
to
co
DC
Unit
9.8 mA
dBm
dBm
kHz
18
Condition
No signal
-3.0dB point
%
AM 30% mod
dB
Kn
DC Test
Kn DC Test
Kn
DC Test
-30dBm is input.
ma
-60dBm is input.
(JA
-100dBm is input.
ma
Center frequency setting R-«
Center frequency setting R*36kO
Center frequency setting R=6.8kn
Center frequency setting R«36kn
ma
25mVrms is input (Pin11)
DC voiiage is input to pinl 3.
DC voltage is input to pinl 3.
5) M64076AGP (XA0352)
XBo
SI
CPS
RST
1 20
2
3 18
4 17
19
GND
Xin
Xout
OP2
a>
Vcc
Fin 1
Lockl
PD1
VT1
VF [10
b
6
7
o
-nI
O)
>
O
U
8 13
9
16
15
14
12
11
OP1
Fin2
Lock2
PD2
VT2
GND
6) NJM2904V-TE1 (XA0573)
Dual Single Supply Operational Amplifier
(Top View)
7) NJM2902V-TE1 (XA0596)
Quad Single Supply Operational Amplifier
A OUTPUT Q
A -IN P U T [ j T
A + INPUT [ T
GND ¡ ~ r
(Top View)
A OUTPUT Q _
A -IN P U T f | 7 -
L ir
A + INPUT [ T
v+ [jT
B +INPUT [~5~-
B - INPUT | 6 [- 1 \ B / \ C
J J V+
~7~[ B OUTPUT
(T ] B -IN P U T
5 l B + IN P U T
14 DOUTPUT
13 I D -INP U T
12 D t INPUT
11 GND
10 C +INP UT
9 C-IN PU T
12
B OUTPUT f T
8 C OUTPUT
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