Alinco DJ195 User Guide
DJ-195
Service Manual
CONTENTS
SPECIFICATIONS
1) GENERAL ................................................................ 2
2) TRANSMITTER ........................................................ 2
3) RECEIVER ............................................................... 2
CIRCUIT DESCRIPTION
1) Receiver System .................................................. 3, 4
2) Transmitter System................................................... 4
3) PLL Synthesizer Circuit ........................................ 4, 5
4) CPU and Peripheral Circuits ................................. 5, 6
5) M3826M8L
SEMICONDUCTOR DATA
1) NMJ2070M T1 (XA210)............................................ 9
2) AT24C16N-10SI-2.7TER (XA0368) .......................... 9
3) M5222FP-600C (XA0385) ...................................... 10
4) TK14521MTL (XA0515).......................................... 11
5) M64082AGP (XA0543)........................................... 12
6) NJM2904V-TE1 (XA0573) ...................................... 12
7) NJM2902V-TE1 (XA0596) ...................................... 12
8) S-81250SG-QD-T1 (XA0619)................................. 13
9) S-80845ALMP-EA9-T2 (XA0620) ........................... 13
10) Transistor, Diode, and LED Ontline Drawings ......... 14
11) LCD Connection (EL0044) .................................... 14
GP (XA0644)................................. 6~8
***
EXPLODED VIEW
1) F ront Vie w............................................................... 15
2) Rear View ............................................................... 16
PARTS LIST
MAIN Unit ......................................................... 17~19
Mechanical Parts.................................................... 20
Packing Parts ......................................................... 20
ADJUSTMENT
1) Required Test Equipment.................................. 21, 22
2) Adjustment Mode ............................................. 23~26
PC BOARD VIEW
MAIN Unit ............................................................... 27
SCHEMATIC DIAGRAM ............................................ 28
BLOCK DIAGRAM ..................................................... 29
ALINCO,INC.
SPECIFICATIONS
1) GENERAL
Frequency coverage T : TX 144 ~ 147.995MHz RX 135 ~ 173.995MHz
E : TX 144 ~ 145.995MHz RX 144 ~ 145.995MHz
EAH : TX 135 ~ 173.995MHz RX 135 ~ 135.995MHz
TFH : TX 150 ~ 173.995MHz RX 135 ~ 173.995MHz
TLH : TX 150 ~ 173.995MHz RX 135 ~ 173.995MHz
Mode F3E (FM)
Channel steps 5,10,12.5,15,20,25, & 30kHz
Memory channels 40 channels+1 CALL channel
Antenna connector BNC (50Ω unbalanced)
Frequency stability ±5 ppm
Microphone input impedance 2kΩ nominal
Power supply requirement 6.0 ~ 16.0V DC (negative ground)
Current drain (at 13.8 V DC) 1.2A (typical) Transmit high at 5W
200mA (typical) Receive at 280mW
50mA (typical) standby
20mA (typical) Battery save on
Usable temperature range -10 ~ +60°C (14 ~ 140°F)
Dimensions 56 (W) × 124 (H) × 40 (D) mm (with EBP-48N)
(Projections not included) 2.2"(W) × 4.88"(H) × 1.57"(D) inches (with EBP-48N)
Weight Approx. 375g (13.2oz) (with EBP-48N)
DTMF 16 Buttons Keypad
Sub audible Tone(CTCSS) encoder/decoder installed (39tones)
Sub audible Tone (DCS) encoder/decoder installed (104codes)
2) TRANSMITTER
Output power Approx. 5W EBP-48N installed
Approx. 5W 13.8V DC
Approx. 0.8W (LOW)
Modulation system V ariable reactance frequency modulation
Spurious emissions Less than -60dB
Max. frequency deviation ±5kHz
3) RECEIVER
Receive system Double conversion superheterodyne
Intermediate frequencies 1st 21.7MHz / 2nd 450kHz
Sensitivity(12dB SINAD) Less than -14.0µdB (0.2uV) [144 ~ 147.995MHz]
Less than -12.0µdB (0.25uV) [135 ~ 173.995MHz]
Selectivity -6dB : 12kHz or more
-60dB : 26kHz or less
Audio output power 280mW (typical with an 8Ω load)
2
200mW (8Ω 10% THD)
CIRCUIT DESCRIPTION
1) Receiver System
The receiver system is a double superheterodyne system with a 21.7MHz first IF and a 450kHz second IF.
1. Front End
The received signal at any frequency in the 130.00- to 173.995-MHz r ange is
passed through thelow-pass filter (L2, L3, L11, C13, C14, C15 and C60) and
tuning circuit (L16 and D15), and amplified by the RF amplifier (Q11). The
signal from Q11 is then passed through the tuning circuit (L17, L18, L19 and
varicaps D13, D14 and D16) and converted into 21.7MHz by the mix er (Q9).
The tuning circuit, which consists of L16, L17, varicaps D15 and D13, L18,
L19, varicaps D14 and D16, is controlled by the tracking v oltage f orm the CPU
so that it is optimized for the reception frequency. The local signal from the VCO
is passed through the buffer (Q13), and supplied to the source of the mixer
(Q9). The radio uses the lower side of the superheterodyne system.
2. IF Circuit
The mixer mixes the received signal with the local signal to obtain the sum of
and difference between them. The crystal filter (XF1, XF2) selects 21.7MHz
frequency from the results and eliminates the signals of the unwanted frequencies. The first IF amplifier (Q10) then amplifies the signal of the selected frequency.
3. Demodulator Circuit
4. Audio Circuit
After the signal is amplified by the first IF amplifier (Q10), it is input to pin 16 of
the demodulator IC (IC5). The second local signal of 21.25MHz (shared with
PLL IC reference oscillation), which is oscillated by the internal oscillation circuit in IC1 and crystal (X1), is input through pin 1 of IC5. Then, these two
signals are mixed by the internal mixer in IC5 and the result is converted into
the second IF signal with a frequency of 450kHz. The second IF signal is output
from pin 3 of IC5 to the ceramic filter (FL1), where the unwanted frequency
band of that signal is eliminated, and the resulting signal is sent back to the IC5
through pins 5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC5, and output as an audio signal
through pin 10.
The audio signal from pin 10 of IC5 is compensated to the audio frequency
characteristics in the de-emphasis circuit (R104, R103, C122, C121) and amplified by the AF amplifier (Q26). The signal is then input to pin 2 of the electronic volume (IC4) f or v olume adjustment, and output from pin 1. The adjusted
signal is sent to the audio power amplifier (IC3) through pin 2 to drive the
speaker.
3
5. Squelch Circuit
2) Transmitter System
1. Modulator Circuit
2. Power Amplifier Circuit
The signal except for the noise component in AF signal of IC5 is cut by the
active filter inside IC. The noise component is amplified and rectified, then converted to the DC voltage to output from pin13 of IC5. The v oltage is led to pin 2
of CPU and compared with the setting voltage. The squelch will open if the
input voltage is lower than the setting v oltage .
The audio signal is conv erted to an electric signal in either the internal or external microphone, and input to the microphone amplifier (IC7). IC7 consists of
two operational amplifiers; one amplifier (pins 5, 6, and 7) is composed of preemphasis and IDC circuits and the other (pins 1, 2, and 3) is composed of a
splatter filter. The maximum frequency deviation is obtained by VR202 and
input to the cathode of the varicap of the VCO, to change the electric capacity
in the oscillation circuit. This produces the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the pre-drive
amplifier (Q4) and drive amplifier (Q3), and input to the final amplifier (Q2). The
signal is then amplified by the final amplifier (Q2) and led to the antenna s witch
(D1) and low-pass filter (L5, L4, L3, L2, C16, C15, C14 and C13), where unwanted high harmonic waves are reduced as needed, and the resulting signal
is supplied to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by D6, converted to DC, and then amplified by a diff erential amplifier. The output voltage
controls the bias voltage from the source of Q2 and Q3 to maintain the transmission power constant.
3) PLL Synthesizer Circuit
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC9) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC1). The oscillated signal from the
VCO is amplified by the buffer (Q5) and input to pin 6 of IC1. Each programmable divider in IC1 divides the frequency of the input signal by N according to
the frequency data, to generate a comparison frequency of 5 or 6.25kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by dividing the 21.25MHz reference oscillation (X1) by 4250 or 3400, according to the
data from the CPU (IC9). When the resulting frequency is 5kHz, channel steps
of 5, 10, 15, 20, 25, 30, and 50kHz are used. When it is 6.25kHz, the 12.5kHz
channel step is used.
4
3. Phase Comparator Circuit
The PLL (IC1) uses the reference frequency, 5 or 6.25kHz. The phase comparator in the IC1 compares the phase of the frequency from the VCO with that
of the comparison frequency, 5 or 6.25kHz, which is obtained by the internal
divider in IC1.
4. PLL Loop Filter Circuit
If a phase difference is f ound in the phase comparison between the ref erence
frequency and VCO output frequency, the charge pump output (pin 8) of IC1
generates a pulse signal, which is converted to DC voltage by the PLL loop
filter and input to the varicap of the VCO unit for oscillation frequency control.
5. VCO Circuit
A Colpitts oscillation circuit driven by Q1 directly oscillates the desired frequency. The frequency control voltage determined in the CPU (IC9) and PLL
circuit is input to the varicaps (D32 and D34). This change the oscillation frequency, which is amplified by the VCO buffer (Q5) and output from the VCO
unit.
4) CPU and Peripheral Circuits
1. LCD Display Circuit
2. Display Lamp Circuit
3. Reset and Backup
4. S(Signal) Meter Circuit
5. DTMF Encoder
The CPU turns ON the LCD via segment and common terminals with 1/4 the
duty and 1/3 the bias, at the frame frequency is 112.5Hz.
When the LAMP key is pressed, “H” is output form pin 50 of CPU (IC9) to the
bases of Q12. Q12 then turn ON and the LEDs (D12 and D17) light.
When the power form the DC jack or e xternal battery increases from Circuits 0
V to 2.5 or more, “H” le v el reset signal is output f orm the reset IC (IC11) to pin
33 of the CPU (IC9), causing the CPU to reset. The reset signal, however,
waits at 100, and does not enter the CPU untilthe CPU clock (X2) has stabilized.
The DC potential of pin 8 of IC5 is input to pin 1 of the CPU (IC9), converted
from an analog to a digital signal, and displayed as the S-meter signal on the
LCD.
The CPU (IC9) is equipped with an internal DTMF encoder. The DTMF signal
is output from pin 10, through R102 and R158 (for le v el adjust-ment), and then
through the microphone amplifier (IC7), and is sent to the varicap of the VCO
for modulation. At the same time, the monitor-ing tone passes through the AF
circuit and is output form the speaker.6. CTCSS Encoder The CPU (IC9) is
equipped with an internal tone encoder. The tone signal (67.0 to 250.3 Hz) is
output form pin 9 of the CPU to the varicap (D3) of the VCO for modulation.
5
6. Tone Encoder
7. DCS Encoder
8. CTCSS, DCS Decoder
9. Clock Shift
The CPU (IC9) is equipped with an internal tone encoder.The tone signal (67.0
to 250.3Hz) is output from pin 9 of the CPU to the varicap (D3) of the VCO f or
modulation.
The CPU (IC9) is equipped with an internal DCS code encoder. The code (023
to 754) is output from pin 9 of the CPU to the varicap (D3) of the PLL reference
oscillator . When DCS is ON, DCS MUTE circuit (Q15-ON, Q18-ON, Q16-OFF)
works. The modulation activates in X1 side only.
The voice band of the AF output signal from pin 10 of IC5 is cut b y sharp active
filter IC8 (VCVS) and amplified, then led to pin 4 of CPU. The input signal is
compared with the programmed tone frequency code in the CPU. The squelch
will open when they match.
In the unlikely e vent that CPU clock noise is present on a particular operating
frequency programmed into the radio , y ou can shift the CPU clock frequency to
avoid the CPU cloc k-noise. The output signal from pin 31 of the CPU turns on
Q30. Then the oscillation frequency of X2 will be shifted about 300 ppm.
5) M3826M8L
***
CPU
Terminal Connection
(TOP VIEW)
GP (XA0644)
6
No. Pin Name Function I/O PU Logic Description
1 P67/AN7 SMT I - A/D S-meter input
2 P66/AN6 SQL I - A/D Noise level input for squelch
3 P65/AN5 BAT I - A/D Low battery detection input
4 P64/AN4 TIN I - A/D CTCSS tone input/DSC code input
5 P63/SCLK22/AN3 BP1 I - A/D Band plan 1
6 P62/SCLK21/AN2 BP2 I - A/D Band plan 2
7 P61/SOUT2/AN1 DCSW O - Activ high DCS signal mute
8 P60/SIN2/AN0 F/M/KEY I - A/D Function/Moniter key input
9 P57/ADT/DA2 CTOUT O - D/A CTCSS
t one output/
DCS
to ne o utput/Tuning voltage out
10 P56/DA1 DTOUT O - D/A DTMF output/ EV R control output
11 P55/CNTR1 SCL O - Pulse Serial clock for EEPROM
12 P54/CNT R0 TBST I/O Pulse/Act iv low T one burst output/UP input whi le tr unking
13 P53/RTP1 BP4 I - - Band plan 4
14 P52/RTP0 MUTE I/O - Activ high Microphone mute/Bank chang e input while trun king
15 P51/PWM3 CLK O - Pulse Serial clock output for PLL,CTCSS,and trunking board
16 P50/PWM0 DATA I/O - Pulse
Serial data output for
PLL,CTCSS
, and tr unki ng boar d/ PLL unloc k si gnal i nput
17 P47/SROY1 STBT I/O - Activ low/Pulse
Trunki ng board det edt i on( when PSW is on) /Storobe signal t o trunki ng board
18 P46/SCLK1 STBP O - Pulse Strobe for PLL IC
19 P45/TX D UTX O - Pulse UART dat a t r ansmission output
20 P44/RXD RTX I - Pulse UART data reception out put
21
P43/
/TOUT
BEEP I/O - Pulse/Activ low Beep tone/Band plan 3(when PSW is on)
22 P42I/NT2 RE2 I Avtiv low
23 P41/INT1 RE1 I Avtiv low
Rotary encoder input
24 P40 SD O - Avtiv low Signal detection output
25 P77 PTT I - Activ high PTT input
26 P76 SDT I Activ high Trunking signal detection input
27 P75 P5C O - Activ low PLL power ON/OFF out put
28 P74 T5C O - Activ low TX power ON/OFF output
29 P73 R5C O - Activ low RX power ON/OFF output
30 P72 AFP O - Activ low AF AMP power ON/OFF output
31 P71 CLSFT O - Activ high CLOCK frequency shift
32 P70/INTO BU I - Activ low Backup signal detection input
33 RESET RESET I - Activ low Reset input
34 Xcin Xcin - - - 35 Xcout Xcout - - - 36 Xin Xin - - - Main clock input
37 Xout Xout - - - Main clock output
38 Vss GND - - - CPU GND
39 P27 PSW I - Avtiv low Power switch input
40 P26 SDA O - Pulse Serial data for EEPROM
41 P25 C5C O - Activ high C5V power ON/OFF output
42 P24 LAMP O - Activ high Lamp ON/OFF
43 P23 KI 0 I Avtiv low
44 P22 KI 1 I Avtiv low
45 P21 KI 2 I Avtiv low
46 P20 KI 3 I Avtiv low
Key matrix input
47 P17 KO3 O - Avtiv low
48 P16 KO2 O - Avtiv low
49 P15/SEG39 KO1 O - Avtiv low
50 P14/SEG38 KO0 O - Avtiv low
Key matrix output
51 P13/SEG37 H/L O - - Tx power H/L
52 P12/SEG36 DA2 O - - DA converter for output power
53 P11/SEG35 DA1 O - - DA converter for output power
54 P10/SEG34 DA0 O - - DA converter for output power
55 P07/SEG33 SCR I - SCR input
7
No. Pin Name Function I / O PU Logic Description
56 P06/SEG32 AFC O - Activ high AF tone control
57 P05/SEG31 S31 O - 58 P04/SEG30 S30 O - 59 P03/SEG29 S29 O - 60 P02/SEG28 S28 O - 61 P01/SEG27 S27 O - 62 P00/SEG26 S26 O - 63 P37/SEG25 S25 O - 64 P36/SEG24 S24 O - 65 P35/SEG23 S23 O - 66 P34/SEG22 S22 O - 67 P33/SEG21 S21 O - 68 P32/SEG20 S20 O - 69 P31/SEG19 S19 O - 70 P30/SEG18 S18 O - 71 SEG17 S17 O - 72 SEG16 S16 O - 73 SEG15 S15 O - -
LCD segment signal
74 SEG14 S14 O - 75 SEG13 S13 O - 76 SEG12 S12 O - 77 SEG11 S11 O - 78 SEG10 S10 O - 79 SEG9 S9 O - 80 SEG8 S8 O - 81 SEG7 S7 O - 82 SEG6 S6 O - 83 SEG5 S5 O - 84 SEG4 S4 O - 85 SEG3 S3 O - 86 SEG2 S2 O - 87 SEG1 S1 O - 88 SEG0 S0 O - 89 Vcc VDD - - - CPU power terminal
90 Vref Vref - - - AD converter power supply
91 Avss Avss - - - AD converter GND
92 COM 3 COM3 O - - LCD COM3 output
93 COM 2 COM2 O - - LCD COM2 output
94 COM 1 COM1 O - - LCD COM1 output
95 COM 0 COM0 O - - LCD COM0 output
96 VL3 VL3 - - 97 VL2 VL2 - - -
LCD power supply
98 C2 I - - - 99 C1 C1 - - - -
100 VL1 VL1 I - A/D LCD power supply
8
SEMICONDUCTOR DATA
1) NMJ2070M T1 (XA210)
Low V oltage Po wer Amplifier
Equivalent Circuit
2) AT24C16N-10SI-2.7TER (XA0368)
16K bits CMOS Serial EEPROM
9
3) M5222FP-600C (XA0385)
Electronic V olume
10
Loading...