Alinco DJ190 User Guide

DJ-190

Service Manual

CONTENTS

+SPECIFICATIONS

2

+CIRCUIT DESCRIPTION

3

+SEMICONDUCTOR DATA

9

+EXPLODED VIEW

15

+PARTS LIST

18

+ADJUSTMENT

21

+PCBOARD VIEW

26

+CIRCUIT DIAGRAM

36

+BLOCK DIAGRAM

43

ALINCO INCORPORATED

e-mail: [e-mail]

TWIN 21 M.I.D. TOWER BUILDING 23F, 1-61, 2-CHOME,
SHIROMI CHUO-KU , OSAKA, 540-8580 JAPAN

Tel [phone] fax [phone]

SPECIFICATIONS

Frequency Coverage

TX

RX

DJ-190T (u.s. Amateur version)

144.000 ~ 147.995MHz 135.000 ~ 173.995MHz

DJ-190E (European Amateur version)

144.000 ~ 145.995MHz 144.000 ~ 145.995MHz

DJ-190TA1 (commercial version VHFL)

135.000 ~ 155.000MHz 135.000 ~ 173.995MHz

DJ-190TA2 (commercial version VHFH)

150.000 ~ 173.995MHz 135.000 ~ 173.995MHz

Channel Step:

5, 10, 12.5, 15, 20, 25, 30kHzsteps

Memory Channels:

40 Channels

Antenna Impedance:

50ohm unbalanced

Frequency Stability:

+/-5 ppm

Microphone Input Impedance:

2kohm nominal.

Signal Type:

F3E (FM)

Offset Range:

0 ~ 99.995MHz

Deviation:

15kHz max.

TX Output (supply voltage):

1.5W (4.8V) / 3.5W (7.2V) / 5W (9.6 ~ 13.8V)

RX Sensitivity:

12dB SINAD better than - 16dBu

RX Selectivity:

-6dB/ +/- 12kHz

I.F.:

(1st) 21.25MHz / (2nd) 450kHz

Power Supply Requirements:

4.8 ~ 13.8V DC (4.8V DC standard)

Current Consumption

Transmitting: Approx. 1.2 Amp. in High Power

at 13.8V DC:

Setting

Receiving: Squelched Approx. 24mA (BS on)

Operating Temperature:

-10 ~ +60*C, 14 ~ 140*F

Dimensions:

57(W) x 151(H) x 27(D) mm

(with EBP-37N without projections)

2 1/4(W) x 6(H) x 1 1/16(D) inches

Weight:

Approx. 300g

Subaudible Tones (CTCSS) :

Encoder installed (50 tones)

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CIRCUIT DESCRIPTION

1) Receiver System

The receiver system is a double superheterodyne system with a 21.7 MHz

first IF and a450 kHz second IF.

1. Front End

The received signal at any frequency in the 130.00- to 173.995-MHz range

is passed through the low-pass filter (L102, L103, L104, C113, C107, C116,

and C114) and tuning circuit (L112 and D107), and amplified by the RF

amplifier (Q107). The signal from Q107 is then passed through the tuning

circuit (L109, L110, L111, and varicapsi D104, D105 and D106) and

converted into 21.7 MHz by the mixer (Q106). The tuning circuit, which

consists of L112, L109, varicaps D107 and D104, Ll110 L111, varicaps

D105 and D106, is controlled by the tracking voltage from the CPU so that

it is optimized for the reception frequency. The local signal from the VCO is

passed through the buffer (Q108), and supplied to the source of the mixer

(Q106). The radio uses the lower side of the superheterodyne system.

2. IF Circuit

The mixer mixes the received signal with the local signal to obtain the sum

of and difference between them. The crystal filter (XF101 , XF102) selects

21.7 MHz frequency from the results and eliminates the signals of the

unwanted frequencies. The first IF amplifier (Q105) then amplifies the

signal of the selected frequency.

3. Demodulator Circuit

After the signal is amplified by the first IF amplifier (Q105), it is input to pin

16 of the demodulator IC (IC104). The second local signal of 21.25 MHz

(shared with PLL IC reference oscillation), which is oscillated by the internal

oscillation circuit in IC102 and crystal (X101), is input through pin 1 of

IC104. Then, these two signals are mixed by the internal mixer in IC104

and the result is converted into the second IF signal with a frequency of 450

kHz. The second IF signal is output from pin 3 of IC104to the ceramic filter

(FL101), where the unwanted frequency band of that signal is eliminated,

and the resulting signal is sent back to the IC104 through pins 5 and 7.

The second IF signal input via pin 7 is demodulated by the internal limiter

amplifier and quadrature detection circuit in IC104, and output as an audio

signal through pin 9.

4. Audio Circuit

The audio signal from pin 9 of IC104 is compensated to the audio

frequency characteristics in the de-emphasis circuit (R162, R161, C172,

C173) and amplified by the AF amplifier (Q109). The signal is then input to

pin 2 of the electronic volume (IC103) for volume adjustment, and output

from pin 1. The adjusted signal is sent to the audio power amplifier (1C105)

through pin 2 to drive the speaker.

5. Squelch Circuit

Part of the audio signal from pin 9 of IC104 is amplified by the noise filter

amplifier consisting of R176, R186, R177, C179, C183, C191, and C194,

and the internal noise amplifier in IC104. The desired noise of the signal is

output through pin 11 of IC104, to be further amplified by the noise amplifier

(Q115). The amplified noise signal is rectified by voltage doublers D109 and

input to pin 4 of CPU (IC5).

Page-3

2) Transmitter System

The audio signal is converted to an electric signal in either the internal or

1. Modulator Circuit

external microphone, and input to the microphone amplifier (IC6). IC6

consists of two operational amplifiers; one amplifier (pins 1, 2, and 3) is

composed of pre-emphasis and IDC circuits and the other (pins 5, 6, and 7)

is composed of a splatter filter. The maximum frequency deviation is

determined to its optimal value by switch circuits consisting of Q9 and Q10

and input to the cathode of the varicap of the VCO, to change the electric

capacity in the oscillation circuit. This produces the frequency modulation.

2. Power Amplifier

The transmitted signal is oscillated by the VCO, amplified by the pre-drive

Circuit

amplifier (Q102) and drive amplifier (Q101), and input to the power module

(IC101). The signal is then amplified by the power module (IC101) and led

to the antenna switch (D101) and low-pass filter (L102, L103, L104, C113,

C107, C116, and C114), where unwanted high harmonic waves are

reduced as needed, and the resulting signal is supplied to the antenna.

3. APC Circuit

Part of the transmission power from the low-pass filter is detected by D103,

converted to DC, and then amplified by a differential amplifier. The output

voltage controls the bias voltage from pin 2 of the power module (IC101) to

maintain the transmission power constant.

3) PLL Synthesizer Circuit

The dividing ratio is obtained by sending data from the CPU (IC5) to pin 2

1.PLL

and sending clock pulses to pin 3 of the PLL IC (IC102). The oscillated

signal from the VCO is amplified by the buffer (Q117) and input to pin 6 of

IC102. Each programmable divider in IC102 divides the frequency of the

input signal by N according to the frequency data, to generate a

comparison frequency of 5 or 6.25 kHz.

2. Reference Frequency

The reference frequency appropriate for the channel steps is obtained by

Circuit

dividing the 21.25 MHz reference oscillation (X101) by 4250 or 3400,

according to the data from the CPU (IC5). When the resulting frequency is

5 kHz, channel stepsof5, 10, 15, 20, 25 and 30 kHz are used. When it is

6.25 kHz, the 12.5 kHz channel step is used.

3. Phase Comparator

The PLL (IC102) uses the reference frequency, 5 or 6.25 kHz. The phase

Circuit

comparator in the IC102 compares the phase of the frequency from the

VCO with that of the comparison frequency, 5 or 6.25 kHz, which is

obtained by the internal divider in IC102

4. PLL Loop Fitter Circuit

If a phase difference is found in the phase comparison between the

reference frequency and VCO output frequency, the charge pump output

(pin 8) of IC102 generates a pulse signal, which is converted to DC voltage

by the PLL loop filter and input to the varicap of the VCO unit for oscillation

frequency control.

Page-4

5. VCO Circuit

A Colpitts oscillation circuit driven by Q301 directly oscillates the desired

frequency. The frequency control voltage determined in the CPU (IC5) and

PLL circuit is input to the varicaps (D301 and D304). This changes the

oscillation frequency, which is amplified by the VCO buffer (Q302) and

output from the VCO unit.

Note

The oscillation frequency is determined by turning Q301 0N and OFF.

Displayed frequencies

Q301

TX: 130.00 - 139.995 MHz

OFF

RX: 130.00 - 161.695 MHz

TX: 140.00 - 173.995 MHz

ON

RX: 161.70 - 173.995 MHz

4) CPU and Peripheral Circuits

The CPU turns ON the LCD via segment and common terminals with 1/3

1. LCD Display Circuit

the duty and 1/3 the bias, at the frame frequency is 85Hz.

2. Display Lamp Circuit

When the LAMP key is pressed, "H" is output from pin 45 of CPU (IC5) to

the bases of Q1 then turn ON and the LEDs (D1, D3) Bight.

3. Reset and Backup

When the power from the DC jack or external battery increases from 0 V to

Circuits

2.5 or more, "H" level reset signal is output from the reset IC (IC2) to pin 35

of the CPU (IC5), causing the CPU to reset. The reset signal. however,

waits at C6 and R98, and does not enter the CPU until the CPU clock (X1)

has stabilized. When the external power drops to 3.2 V or below, the output

signal from the backup IC (IC3), which has been input to pin 34 of the CPU,

changes from "H" to "L" level. The CPU will then be in the backup state.

4. S(Signal)Meter Circuit

The DC potential of pin 13 of IC104 is input to pin 3 of the CPU (IC5),

converted from an analog to a digital signal, and displayed as the S-meter

signal on the LCD.

5. Tone Encoder

The CPU (IC5) is equipped with an internal tone encoder. The tone signal

(67.0 to 254.1 Hz) is output from pin 11 of the CPU to the varicap of the

VCO for modulation.

Page-5

5) CPU Terminal Functions: M38267M8L (XA413)

Page-6

No.

Pin Name

Signal

I/0

Logic

Description

No.

Pin Name

Signa1

I/0

Logic

Description
1

C1C1---51P15/SEG39

F/KEY

I

Active low

Function key input
2

VL1

VL1IA/D

LCDpowersupply

52

P14/SEG38

K10I-3P67/AN7

SMTIA/D

S-meterinput

53

P13/SEG37

K11I-4P66/AN6

SQLIA/D

Noise level input for squelch

54

P12/SEG36

K12I-5P65/AN5

BATIA/D

Low battery detection input

55

P11/SEG35

K13l-6P64/AN4

BP5IA/D

Band plan5

56

P11/SEG34

K14I-

Key matrix input
7

P63/CLK22/AN3

BP4IBand plan4

57

P07/SEG33

SFTO-

VCO frequency range change
8

P62/CLK21/AN2

ULIActivehigh

PLL unlock signal input

58

P06/SEG32

SDOActive low

Signa detection output
9

P61/SOUT2/AN1

BP1,2IA/D

Band plans 1 and 2

59

P05/SEG31

AFCOActive high

AF tone control output
10

P60/SIN2/ANO

MOMIActivelow

Monitor key input

60

P04/SEG30

DA4O-11P57/ADT/DA2

CTOUT

O

D/A

CTCSS tone output

61

P03/SEG29

DA3O-12P56/AD1

DTOUT

O

D/A62P02/SEG28

DA2O-

DA converter for electronic volume and output power
13

P55/CNTR1

TSQDIActivelow

CTCSS tone detection input

63

P01/SEG27

DA1O-14P54/CNTRO

BEPOPulse

Beep tone output/Band plan 3

64

P00/SEG26

DA0O-15P53/RTP1

STB2

I/O

Active low/pulse

CTCSS unit detection/Strobe signal to CTCSS unit

65

P37/SEG25

S25O-16P52/RTP0

MUTE

I/O

Activehigh

Microphone mute

66

P36/SEG24

S24O-17P51/PWM1

CLKOPulse

Serial clock output for PLL, CTCSS

67

P35/SEG23

S23O-18P50/PWM0

DATAOPulse

Serial data output for PLL CTCSS

68

P34/SEG22

S22O-19P47/SRDY1

ACK

I/0

Pulse

Band plan 6

69

P33/SEG21

S21O-20P46/SCLK1

STB1OPulse

Strobe for PLL IC

70

P32/SEG20

S20O-21P45/TXD1

UTXOPulse

UART data transmission output

71

P31/SEG19

S19O-22P44/RXD1

URXIPulse

UART data reception input

72

P30/SEG18

S18O-23P43/D/TOUT

TBSTOPulse

Tone burst (1750Hz) output (European version)

73

SEG17

S17O-24P42/INT2

RE2IActivelow

74

SEG16

S16O-25P41/1NT1

RE1IActivelow

Rotary encoder lnput

75

SEG15

S15O-26P40

PTTIActivehigh

PTT input

76

SEG14

S14O-27P77

DSWOActivelow

77

SEG13

S13O-28P76

STD

I/O

Activehigh

Deviation adjustment during transmission

78

SEG12

S12O-

LCD segment signal
29

P75

DSDIPulse

Deviation adjustment during transmission

79

SEG11

S11O-30P74

T3COActive low

TX power ON/OFF output

80

SEG10

S10O-31P73

P3COActive low

PLL power ON/OFF output

81

SEG9S9O

-32P72

AFPOActivelow

AFAMP power ON/OFF output

82

SEG8S8O

-33P71

R3COActivelow

RX power ON/OFF output

83

SEG7S7O

-34P70/INT0

BUIActivelow

Backup signal detection input

84

SEG6S6O

-35RESET

RSTIActivelow

Resetinput

85

SEG5S5O

-36XCIN

XCIN---86

SEG4S4O

-37XCOUNT

XCOUT

---87SEG3S3O

-38XIN

XIN--

Main clock input

88

SEG2S2O

-39XOUT

XOUT--

Main clock output

89

SEG1S1O

-40VSS

GND--

CPU ground

90

SEG0SOO

-41P27

PSWIActivelow

Power switch input

91

VCC

VDD--

CPU power terminal
42

P26

SCLOPulse

Serial clock for EEPROM

92

VREF

VREF--

AD converter power supply
43

P25

C3COActivehigh

C3 power ON/OFF output

93

AVSS

AVSS--

AD converter ground
44

P24

SDAOPulse

Serial data for EEPROM

94

COM3

COM3--

-45P23

LMPOActivehigh

Lamp ON/OFF

95

COM2

COM2O-

LCD COM2 output
46

P22

T/KEY

I

Activelow

Tone burst/LPTT input

96

COM1

COM1O-

LCD COM1 output
47

P21

K00

I/O-Band plan BP7 input

97

COM0

COM0O-

LCD COM0 output
48

P20

K01O-

Key matrix output

98

VL3

VL3I-

LCD power supply
49

P17

K02O-99VL2

VL2I-

LCD power supply
50

P16

K03O-

100C2I--

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