Alinco DJ-1400 Service Manual

DJ-180 DJ-1400

Service Manual

CONTENTS

SPECIFICATIONS PC BOARD VIEW

1) General 2 1) VCO Unit 24

2) Transmitter. 2 2) JACK Unit 24

3) Receiver 2 3) PTT Unit Side B 24

4) Functions for Each Version 3 4) PS Unit 25

CIRCUIT DESCRIPTION 5) ROM1 Unit Side B 25

1) Receiver System 4 6) ROM2 Unit Side B 25

2) PLL VCO Circuit. 5 7) RF Unit Side A 26

3) Transmitter System 5 8) RF Unit Side B 27

4) DTMF Encoder Circuit (option). 6 9) CPU Unit Side A. 28

5) Tone Squelch Circuit (option) 6 10) CPU Unit Side B 29

6) Microprocessor and Peripheral Circuit 6 11) RE Unit 30

7) Terminal Function of Microprocessor 7 12) CTCSS UniL 30

SEMICONDUCTOR DATA 13) DTMF Unit. 31

1) LR408721 10 PARTS LAST

2) M5218FP 10 CPU unit 32

3) M5236ML. 10 PS unit. 32

4) MB1504LPF 11 ROM1 Unit 33

5) MC3357 11 DTMF Unit 33

6) MX365 12 RF Unit 33 ~ 36

7) NJM386 13 Vco unit 37

8) RH5VA32AA. 13 CTCSS Unit 37

9) RH5VA45AA. 13 PTT SW Unit 38

10) X24C01A 14 JACK Unit 38

11) X24C04S14 14 RE Unit 38

12) X24C16S14 14 Others 38

13) Transistor, Diode and LED Outline Draw 15 ROM2 Unit. 38

14) LCD Connection. 16 PACKING 38

EXPLODED VIEW Parts Table for Each Version. 39

1) Rear Case 1 17 ADJUSTMENT

2) LCD 17 1) Required Test Equipment. 40

3) Rear Case 2 18 2) Before Adjustment 40

4) Front Case 1 19 3) Adjustment for DJ180, DJ1400 41

5) Front Case 2 20 4) Adjustment for DJ1400AN/QN 42

6) Front Case 3 and Battery Terminal 21 5) Adjustment Quick Reference 43

7) Ten Key Cover and Key Pad Panel 22 6) Adjustment Points. 43 ~ 44

8) CTCSS Unit and ROM1 Unit 23 CIRCUIT DIAGRAM 45 ~ 46 BLOCK DIAGRAM 47

ALINCO INCORPORATED

TWIN 21 M.I.D. TOWER BUILDING 23F, 1-61, 2-CHOME, SHIROMI CHUO-KU , OSAKA, 540-8580 JAPAN

Tel (81)6-6946-8150 fax (81)6-6946-8175 e-mail: export@alinco.co.jp

SPECIFICATIONS

DJ-180

1) General Frequency Coverage:

RX: 137.000 ~ 173.995MHz (T, TM version)

TX: 144.000 ~ 147.995MHz (T, TM version)

RX: 137.000 ~ 173.995MHz (TA, TB, TA2, TB2 version)

TX: 137.000 ~ 173.995MHz (TA, TB, TA2, TB2 version)

RX/TX: 144.000~145.995MHz(TS, TSA, TZ, E, EA, EB version)

Frequency Resolution: Memory Channels:

Antenna Impedance: Signal Type:

Power Supply Requirement: DC 5.5V~13.8V (Rated 7.2V Ni-Cd) Dimensions: Approximately 132(H) x 58(W) x 33(D) mm

Weight : Approximately 350g

2) Transmitter Output Power.I 5.0W with Optional 12V Ni-Cd Battery

Modulation System: Max. Frequency Deviation:

Tone Frequency:

DTMF Encoder:

Tone Burst:

5, 10, 12.5, 15, 20, 25kHz steps

10 Channels (standard)

50 ohm unbalanced

F3E(FM)

2.0W with Standard 7.2V Ni-Cd Battery (144.000~147.995MHz) (160.000~165.000MHz)... TA2, TB2 only

Variable Reactance Frequency Modulation +/ -5kHz

67.0 to 250.3Hz -38 Subaudible Encoding Tones (E, EA, EB version: option)

(TZ, EB version: option)

(E, EA, EB version only)

3) Receiver Receiver System: Double-Conversion Superheterodyne Intermediate Frequency.' 1st IF: 21.4MHz

2nd IF: 455kHz

Sensitivity: 12dB SINAD less than -10dBu

(144.000~17.995MHz) (160.000~165.000MHz)... TA2, TB2 only

Page 2

SPECIFICATIONS

DJ-1400QN / AN (The Narrow Version)

1) General Frequency Coverage:

136.GGG ~ 155.000MHz (AN version)

150.000 ~ 173.995MHz (QN version)

Frequency Resolution: Memory Channels:

Antenna Impedance: Signal Type:

Power Supply Requirement: DC 5.5V~13.BV (Rated 7.2V Ni-Cd) Dimensions:

Weight :

2) Transmitter Output Power.I 5.GW with Optional 12V Ni-Cd Battery

Modulation System: Max. Frequency Deviation:

Tone Frequency:

Time Out Timer Time Out Penalty

3) Receiver

Receiver System: Intermediate Frequency.'

Sensitivity:

AF Output

5, 10, 12.5, 15, 20, 25kHz steps

10 Channels (standard)/option 50 and 200ch

50 ohm unbalanced

F3E(FM)

Approximately 132(H) x 5B(W) x 33(D) mm Approximately 35Gg

2.GW with Standard 7.2V Ni-Cd Battery

Variable Reactance Frequency Modulation +/ -2.5kHz

67.0 to 250.3Hz -38 Subaudible Encoding Tones 0 to 450 sec 0 to 15 sec

Double-Conversion Superheterodyne 1st IF: 21.4MHz

2nd IF: 455kHz

12dB SINAD less than -16dBu

200mW (10% THD)

Page 2-1

4) Functions for Each Version RX

Function

Version

Frequency Range

DJ-180T 130~174 144~148 x DJ-180TA 130~174 130~174 x DJ-180TA2 130~174 130~174 x DJ-180TB 130~174 130~174 x DJ-180TB2 130~174 130~174 x DJ-180TM 130~174 144~148 x DJ-180TS

144~146 144~146 x DJ-180TSA 144~146 144~146 x DJ-180TZ 144~146 144~146 x DJ-180E 144~146 144~148 DJ-180EA 144~146 144~146 DJ-180EB 144~146 144~146 DJ-1400 130~174 130~174 x DJ-1400A 130~174 130~174 x

Frequency Range(facto

Tone

Burst

CTCSS

A(option)

O A(option)

A(option) x R

Final Operatio

DTMF BAND O O O O O O O O O O O O

R+LA R+LA

H R+LA

R+LA

H R+LA

R+LA O O O O O x(with16keys) R

O O

x R+LA x R+LA

R R

DJ-1400B 130~174 130~174 x X x R+LA DJ-1400F 130~174 130~174 x DJ-1400G

130~174 130~174 x X x R+LA DJ-1400TM 130~174 130~174 x DJ-1400AN 136~155 130~174 x DJ-1400QN 150~174 130~174 x

O O

x R+LA x R+LA

Final Operation R: Press and hold the "F" key and turn on the radio. R+LA: Press and hold the "F" and "LAMP" keys and turn on the radio.

Note: The expanded frequency will return to the initial setting' if you reset the radio with.."R" operation after 'R + LA'' operation. To resume the expanded frequency . reset the radio again with..R + LA" operation.

Page 3

CIRCUIT DESCRIPTION

1) Receiver System The receiver system is the double superheterodyne. The first IF is 21.4MHz andthe second IF is 455kHz.

1. Front End

2. First Mixer

3. IF Amplifier

4. Audio Circuit

The signal from the antenna is passed through a low-pass fitter and input to the RF coil L4. The signal trom L4 is amplified by Q1 and led to the band passtilter (L5, L6,

L7), and led to the first mixer gate of Q2.

The amplified signal (fo) by Q1 is mixed with the first local oscillator signal (fo -21.4MHz) from the PLL circuit by the first-stage mixer Q2 and so is converted into the first IF signal. The unwanted frequency band of the first IF signal is eliminated by the monolithic crystal filter (XF1), and led to IF amplifier Q3.

The first IF signal is amplified by Q3, and inputto pin16 of IC1, where it is mixed with the second local oscillator signal (21.855MHz) and so is con verted into the second IF signal (455kHz). The second lF signal is output from pin3 of IC1, and unwanted frequency band of the second lF signal is eliminated by a ceramic filter (FL1). The resulting signal is then amplified by the second lF limiting amplifier, and detected by quadrature circuit. The audio signal is output from ping of IC1.

The detected signal from IC1 is passed through the low-pass filter and led to the flat amplifier Q13. When the optional Tone Squelch unit is equipped, the tone signal is eliminated by lC701. Q13 is switched ON/OFF by AFC slgnal from CPU. The audio signal is input to the main volume (VR3) and amplified by the power amplifier IC3 to drive the speaker. The power supply voltage of IC3 is limited by AF regulator consisting of Q14 and Q15 to prevent the speaker from overdriving. The power supply voltage of IC3 is switched ON/OFF by AFP signal.

5. Squelch Circuit

The noise in the audio signal from IC1 is passed through the squelch control variable resistor (VR4) and input to pin10 of IC1. The audio signal is ampli fied by filter amplifier of IC1 and output to pin11. The desired noise of the audio signal is eliminated by the high-pass filter and amplified by Q12. The resulting signal is rectified by D13 and then input to pin12 of IC1. When the squelch circuit is close, pin13 of ICl goes to "low". When the squelch circuit is open or a signal is received, pin13 goes to "high", then the signal of pin13 is led to CPU.

Page 4

2) PLL, VCO Circuit Output frequency of PLL circuit is set by the serial data (pin9: clock, pin10: data, pin11 : toad enable) from microprocessor.

PLL circuit consists of v Co Q201, buffer amplifier Q202 and Q17. When PLL is locked, pin7 of IC2 goesto "high" and UNLOCK SW Q19 becomes OFF, then T.MUTE signal goes to "low". The pulse wave output of charge pump is converted to DC voltage by PLL

loop filter circuit, and supplied to D201 , D202 of varicap diode in VCO unit. The VCO tune voltage is applied to the varicaps D3, D4, D5 and D6 in the frontend. The frequency modulation is executed when the audio signal voltage is supplied to the varicaps D201, D202 and D203.

3) Transmitter System

1. Microphone The voice from the internal or external microphone is led to the pre-empha- Amplifier sis circuit, and then input to the microphone amplifier IC4, which consists of

two operational amplifiers. The amplified signal is input to the low.pass filter lC4. The output from the microphone amplifier is passed through variable resis tors VR2 tor modulation adjustment to varicap diode of the VCO, contromng the VCO frequency.

2. Power Amplifier The signal from VCO is amplified by buffer amplifiers Q4 and Q5, and input to the buffer amplifiers Q6 and input to the power amplifier Q7. The amplified signal is output from Q7, and then passed through the low-pass filter, the an tenna switch circuit and the output low-pass tilter. The unwanted harmonies frequency signal is eliminated by the low-pass fitter and input to the antenna. The LC matching circuits located between amplifiers of the transmitting circuit make the transmission smooth.

3. Automatic Power

Control Circuit The automatic power control(APC) circuit is used to obtain a stable transmis

sion power. This circuit detects the transmission power by D8 in the low- pass filter consisting of L18, L19, C59, and C64. The detected DC voltage is supplied to APC circuit. When the detected voltage goes higher than the settled voltage, the bias voltage of APC amplifier Q9 goes to low. The collector voltage of APC amplifier Q10 goes to low and the power supply voltage of Q5 goes to low, and output power becomes small to prevent from the over power. At low power the Power Control Switch Q8 lets the base voltage of APC

DET Q11 and the collector voltage of APC AMP Q10 down, also switches

between high power and low power, and inhibits the transmission.

Page 5

4) DTMF Encoder Circuit (option) The DTMF signal corresponding to the combination of the column and row is output from tone output pin17 of IC401 Encoder, producing a frequency- modulated RF output. The Q401 switches the DTMF Encoder when lC401 is active during DTMF transmission.

5) Tone Squelch Circuit (option)

1.Decoder The second IF signalfrom pin11 of IC1, and input to the tone squelch decoder lC701. When the tone squelch decoder IC701 decodes the input tone signal fre quency as the programmed frequency, pin13 goes to "Low". The signal is input to pin16(DET) of lC107, and the squelch goes off. When the Tone squelch decoder IC701 does not decode the input tone signal frequency as the programmed frequency, pin13 goes to "High".

2. Encoder The tone signal is output from pin16 of IC701, producing a frequency-

modulated RF output.

6) Microprocessor (CPU) and Peripheral Circuit

Refer to "Terminal Function of Microprocessor" about each terminal func

tion.

1, BS Mode When the Squelch is closed for more than 5 seconds, the radio goes into the

BS(Battery Save) mode automatically. Pin11 (R5C) and pin19 become High

or Low periodically. Open the Squelch, and the radio does not go into the

BS mode.

2. Backup Reset When the voltage detector circuit lC303 detects a decrease in the C5V line, CPU RAM data is stored in the EEPROM IC, IC601. IC 302 is also the voltage detector circuit and it detects the lower voltage than IC303. The circuit detects a increase in the C5V line when power is turned on, and then the CPU will be initialized.

3. Reset

Press and holdthe."F" key, then turn on the power. The radio will reset to

initial factory settings.

Even if you expanded the frequency, it will return to the initial setting. To resume the expanded frequency, press and hold the "F" and "Lamp" keys, then turn on the power.

Page 6

7) Terminal Function o f Microprocesser Name I/O Description PinNo. PinName H L TBST O 1750Hz Tone Burst Output 9 P57/PWM3 Normal:H(HiZ) Output:Pluse BEEP O Beep Tone Output 10 P56/PW M 2 Normal:H(HiZ) Output:Pluse R5C O RX 5V ON/OFF 11 P55/PWM1 ON OFF T5C O TX5V ON/OFF 12 P54/PWM0 ON OFF AFP O AF Power Amplifier ON/OFF 13 P53/SIG ON OFF AFC O IF Mute Output 14 P52/CNT2 Mute OFF Mute ON

M.MUTE O Microphone Mute Output 15 P5l/CNT1 RE1 I Rotary Encoder Input 1 16 P50/INT3 LAMP O Lamp ON/OFF Switch 17 P37/SR DY ON OFF BAT I Battery L ow Indicator Input 18 P36/CLK Low Normal P5C O PLL Power ON/OFF 19 P35/SOUT ON OFF EICD I EEPROM Unit Detection 20 P34/SIN Equipped Nothing XW R I External EEPROM Write Cycle Detection 21 P33rr Normal Write cycle RE2 I Rotary Encoder Input 2 22 P32/INT2 SCOM O Band Plan Scan Output 23 P3l/XCIN H(Hiz) Low Active P.H/L O Transmit Power Switch 24 P30/XCOUT L ow Power High Power BU I Back up Mode Input 25 INT1 Normal Negative Edge Triggered

RES I Reset Input 27 RESET at Work on Reset

TSQD I Tone Detecton Input 31 P17 Undetected Detected TICD I Tone Unit D etection 32 P16 Nothing Equipped BP1 I Band Plan(TX) 33 P15 Expanded Normal BP2 I Band Plan(RX) 34 P14 Expanded Normal BP3 I Band PIan(TX,RX) 35 P13 Expanded Normal BP4 I Band Plan(Channelstep) 36 P12 Expanded Normal BP5 I Band Plan(OffsetFreq.) 37 P11 Expanded Normal CH I Band Plan(ChanneIDisp.) 38 P10 Expanded Normal SLC O CIock for EEPROM IC 39 P07 Normal:Hiz Output: Pluse SDA I/O Data for EEPROM IC 40 P06 Normal:Hiz Output: Pluse CLK O Clock for PLL,TONE IC 41 P05 Output:Pluse Normal:L DTA O Data for PLL,TONE IC 42 P04 Output:Pluse Normal:L STB1 O Strobe for PLL IC 43 P03 Output:Pluse Normal:L STB2 O Strobe for TONE IC 44 P02 Output:Pluse Normal:L FUNC I Function Key Input 45 P0l OFF ON SD I Signal Detection Input 46 P00 Received Nothing TBST I Tone Burst Key Input 47 P27 OFF ON CALL I CALL(APO) 48 P26 OFF ON LAMP I LAM P (FLJPL) 49 P25 OFF ON MONI I M ONl(P.H/L) 50 P24 OFF ON TONE I TONE(MW ) 51 P23 OFF ON V/M T.SCAN I T.SCAN(CH STEP) 53 P2l OFF ON PTT I PTT K ey Input 54 P20 OFF ON

COMO O Common Output 58 COM0 COM1 O Common Output 59 COM1 COM2 O Common Output 60 COM2

SEGO O Segment Output 62 SEGO SEG1 O Segment Output 63 SEGl SEG2 O Segment Output 64 SEG2 SEG3 O Segment Output 65 SEG3 SEG4 O Segment Output 66 SEG4 SEG5 O Segment Output 67 SEG5 SEG6 O Segment Output 68 SEG6 SEG7 O Segment Output 69 SEG7 SEG8 O Segment Output 70 SEG8 SEG9 O Segment Output 71 SEG9 SEG1O O Segment Output 72 SEG10 SEG11 O Segment Output 73 SEG11 SEG12 O Segment Output 74 SEG12/P43 SEG13 O Segment Output 75 SEG13/P42 SEG14 O Segment Output 76 SEGl4/P4l SEG15 O Segment Output 77 SEG15/P40 SEG16 O Segment Output 78 SEG16/IN7 SEG17 O Segment Output 79 SEG17/IN6 SEG18 O Segment Output 80 SEG18/IN5 SEG19 O Segment Output 1 SEG19/1N4 SEG2O O Segment Output 2 SEG20/IN3 SEG2l O Segment Output 3 SEG21/IN2 SEG22 O Segment Output 4 SEG22/IN1 SEG23 O Segment Output 5 SEG23/IN0

Clock Input 3.58MHz 28 XIN Clock Output 3.58MHz 29 XOUT Ground 30 Vss

I V/M(OFFSET) 52 P22 OFF ON

Ground 6 AVss +4V 7 Vref +4V 8 Vcc

26 CNVss

55 VL3 56 VL2 57 VL1

61 COM3

during Tone Burst Tansmission Normal

Page 7

SEMICONDUCTOR DATA

1) LR408721 (XA0042)

Tone Dialer

V+[

1 ^ 18

1 Non Connect

Test Circuit

3.5-1 OV 0 LR408721

3.58MHz JT~

—IDhj—

----

1 18

3 16 4 5 14

6 13

8 11

2) M5218FP (XA0068)

Dual Low Noise

Operational Amplifiers

Row Tone 400mV rms ColumnTone 500mV rms

-O

f1=697Hz f2=770Hz f3=852Hz f4=941 Hz f5=1209Hz f6=1336Hz f/= 14 //H z f8=1633Hz

XMRT I Switch

COL1 d

COL2I

COL3 [

OSCin

OSCout

Output 1

V+I

1 l=

2 17

3 16

4 ^ 15

5 co 14

's! I\J

6 - 1 13

7 12

8 11

9 10 Z D COL4

1 Tone out

1 Single Tone Inhibit

Z D ROW1

Z D ROW2

Z D ROW3

Z D ROW4

I Mute Out

| 8 Power Supply Plus

3) M5236ML (XA0104)

Voltage Regulator

Test Circuit

Inverting Input 1

Non Inverting Input 1

Power Supply Minus

2 IZ Z

3 1=

4 IZ Z

r r m r

VREF GND VIN

M5236ML

| 7 Output 2

| 6 Inverting Input 2

| 5 Non Inverting Input 2

4) MB1504LPF-G-BND-TF (XA0145)

Frequency Synthesizer

Function Table

FC input P.D.input

Do output

High or Low

Reference oscillator input terminal

Reference oscillator output terminal

Power supply terminal for

r h a r n e m im n

w. y w

Power supply terminal 3V 15mA

Charge pump output terminal

Ground terminal

Phase detector output terminal I D t when locked: LD=H

Prescaler input terminal

OSCinl— 1

OSCout I—

Vp C Z

Vcc I

noi—

GNDI

fin C ^

High High

Low Low

---

fr=fp HiZ fr>fp High fr<fp

Low fr>fp Low fr<fp

High

JoR

I0P

Ifp

Z J F C

I LE

I Data Serial data input

I Clock

Phase detector output terminal for external

charge pump

Phase detector output terminal for external charge pump

Programmable divider output terminal

Reference divider output terminal

Phase switch input terminal of phase comparator

Load enable signal input terminal

terminal

Clock input terminal

5) MC3357 (XA0063)

Narrow Band FM IF IC

Vcc=6V

F=10.7MHz

3mA

Icc Limit

5|iV 350mV

-3dB Dev=+/-3KHz

6) MX365 (XA0203)

CTCSS Encoder/Decoder

---

1 I I 2

33p a P ,

1MHz

MX365ADW

Vdd

Xtal Clock inpul

---

Xtal Load /Latch

D5 D4

D3 D2

D1 DO RX DETECT

Vss COMP.REF

TONE IN

RX AUD IN

BIAS

TX AUD OUT

RX AUD OUT

PTL

RX/TX

TONE OUT

DECODE COMP IN

RX DECODE

i 4 23

¥ -

0.1*iF

0.1 H F

0 4 7 ^ F

11 1

0 1^ F " r

0 1^F

0.1(.iF

56 0 K

~ p ° n

1 1 1 "

I s

Decode Comparator Ref: This pin is internally biased to VDD/3 or 2VDD/3 via 1M resistors depending on the

logical state of the Rx Tone Decode Out pin. Rx Tone Decode Out = 1 will bias bias this input 2VDD/3; a logic "0" will bias this input VDD/3. This input provides the decode comparator reference voltage, and switching of

bias voltages provides hysteresis to reduce "chatter" under marginal conditions.

RX Tone Decode Out: This is the gated output of the decode comparator. This output is used to gate the RX Audio path. A logic "0" on this pin indicates a successful decode and that the Decode Comparator Input pin is

more positive than the Decode Comparator Ref. input.

Decode Comparator Input: This is the inverting input of the decode comparator. This pin is normally

connected to the integrated output of the Rx Tone Detect

line.

Rx Tone D etect: In Rx mode this pin will go to logic '11

during a successful decode. It must be externally

integrated to control response and deresponse times.

Tx Tone Out: The CTCSS sinewave output appears on this pin under the control of the Rx/Tx pin. This pin,

when not transmitting a tone, may be biased to VDD/2 -

0.7V or O/C .

Rx/Tx: This input (in parallel mode) selects Rx or Tx modes . In serial mode this function is serially loaded.

This pin is internally pulled to VDD via a 1 M ii resistor.

PTL: in paraiiei Rx mode this pin operates as a 'Press To Listen' function by enabling the Rx audio path, thus

overriding the tone squelch function. In parallel Tx mode this pin reverses the phase of the transmitted CTCSS tone (used for squelch tail elimination). In serial mode this function is serially loaded.

Rx Audio Out: This is the high pass filtered receive audio output pin. This pin outputs audio when Rx TONE

DECODE = 0, or PTL = 1, or when Notone is programmed. In Tx mode this pin is biased to VDD/2.

Tx Audio Out: This is the high pass filtered transmit audio output pin. In Tx mode this pin outputs audio

present at the Tx Audio Input pin. In Rx mode this pin is biased to VDD/2.

Bias: This pin is the output of an internally generated

VDD/2 bias level and would normally be externally decoupled to Vss via C7.

Tx Audio In: This Is the Tx Audio input pin. In Tx mode It may be prefiltered, using the Tx audio path, thus

helping to avoid talk off due to intermodulation of speech frequencies with the transmitted CTCSS tone. This pin

is internally biased to VDD/2.

Rx Audio In: This Is the input to the audio high pass filter in Rx mode. It is internally biased to VDD/2.

Tone Input: This is the Input to the CTCSS tone detector. It is Internally biased to VDD/2.

7) NJM386 (XA0061)

Dual Power Amplifiers

V+=9V RL=16£2 Po=500mW

V+

8) RH5VA32AA-T1 (XA0198)

C-MOS Voltage Detector

/> N

____

C\J

U U ..EF

OUT VDD VSS

Gain

-Input

+lnput

GND

1 1=

2 d

3 C

4 [ =

I Z I 8

1=17

= □ 6 Vs

= □ 5

Equivalent Circuit

Gain

Bypass

Vout

RH5VA32AA

9) RH5VA45AA-T1 (XA0208)

C-MOS Voltage Detector

in Û

u u.nr

OUT VDD VSS

RH5VA45AA

Equivalent Circuit

10) X24C01A (XA0199)

EEPROM 1024Bit

Pin Names

AO Vcc

X24C01A

Vss

SCL

SDA

11) X24C04S14 (XA0200)

EEPROM 4096Bit

NC NC

AO Vcc

A1 TEST

X24C04

SCL

AO - A2 SDA Serial Data SCL Serial Clock WC Vss Vcc

Address inputs

Write Control Ground +5V

Pin Names

AO ~ A2 SDA Serial Data SCL TEST Vss Vcc NC

Address inputs

Serial Clock Hold at Vss Ground +5V No Connect

Vss SDA

NC NC

12) X24C16S14 (XA0201)

EEPROM 16384Bit

NC NC

Vss

X24C16

Vcc

TEST

SCL

SDA

Pin Names

AO ~ A2

SDA SCL Serial Clock TEST Vss Vcc

Address inputs Serial Data

Hold at Vss Ground +5V No Connect

13) Transistor, Diode and LED Outline Drawings

O S

S17

S16

S14

S13 _

S12

S10

@ c o

^ 5 4 !

S18

S21

S22

S23

S19

S15

S11

COMO

COM1

^om CQ

COM2

+ 32 hidden pages