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435FX
Service Manual
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Alinco 435FX, DR-135 Service Manual

DR-135/435FX
S e r v i c e M a n u a l
C O N T E N T S
SPECIFICATIONS
GENERAL
TRANSMITTER..........................................
RECEIVER
CIRCUIT D ISC RE TION
1) Receiver System DR-135..............................
2) Transmitter System DR-135
3) PLL Synthesizer Circuit DR-135
4) Receiver System DR-435
5) Transmitter System DR-435
6) PLL Synthesizer Circuit DR-435.............
7) CPU and Peripheral Circuit
8) Power Supply Circuit
9) M38268MCA075GP (XA1130)
SEMICON DUC TOR DATA
1) NJM7808FA(XA0102)
2) TC4S66F (XA0115)
3) AN8010M (XA0119).....
4) TC4W53FU(XA0348)
5) TA31136FN (XA0404)
6) LA4425A (XA0410)........................................
7) BR24L32FJ (XA0604Z)
8) S-80845ALMP (XA0620)
9) S-816A50AMC (XA0925)
10) NJM78M05DL1 A(XA0947)
11) LM2904PWR (XA1103)...
12) LM2902PWR (XA1106)..................................
13) MB15E07SR (XA1107)...................................
14) RA60H1317M1 (XA1108)
15) S-AU82L (XA1142).........................................
16) Transistor, Diode and LED Outline Drawing...
17) LCD Connection (TTR3626UPFDHN)
EXPLO DED VIEW
1) Top and Front View........................................
2) Bottom View...................................................
3) LCD Assembly.................................
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PARTS LIST
2 2 2
3,4
4 4,5 5,6 6,7
7
8
8
9-11
CPU Unit................................................. 24
MAIN Unit DR-135
MAIN Unit DR-435.
Mechanical Parts.........
Packing Parts
ACCESSORIES.......;.......................... 31
ACCESSORIES (SCREW SET)
............................ 24-27
....
........................... 27-30
........................
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............
30
31 31
DR-135 ADJUSTMENT
1) Adjustment Spot
2) VCO and RX Adjustment Specification.. 33
3) TX Adjustment Specification
4) RX Test Specification............................ 34
5) TX Test Specification............................ 35
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32
33
DR-435 ADJUSTMENT
12 12 12 12
.
13 13 14 14 14 14 15 15 16 17 18 19
20
21 22
23
1) Adjustment Spot
2) VCO and RX Adjustment Specification.. 37
3) TX Adjustment Specification
4) RX Test Specification
5) TX Test Specification... ...
PC BOARD VIEW
1) CPU Unit Side A DR-135 (UP0538A).... 41
2) CPU Unit Side B DR-135 (UP0538A).... 41
3) CPU Unit Side ADR-435 (UP0545)
4) CPU Unit Side B DR-435 (UP0545)...... 42
5) MAIN Unit Side A DR-135 (UP0538A)... 43
6) MAIN Unit Side B DR-135 (UP0538A).. 43
7) MAIN Unit Side A DR-435 (UP0545)..... 44
8) MAIN Unit Side B DR-435 (UP0545).... 44
SCHEMATIC DIAGRAM
1) CPU Unit DR-135
2) CPU Unit DR-435
3) MAIN Unit DR-135
4) MAIN Unit DR-435
................................... 36
............ . 38
........
................... 39
....................
.....,......
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..................
................................ 48
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40
42
45 46
47
BLOCK DIAGRAM
1) DR-135................................................. 49
2) DR-435................................................. 50
A L I N G O, inc
SPE C I F I C ATI ON S
■ General
Frequency coverage DR-135 DR-435 FX
FXE
Operating mode FM 16K0F3E ( Wide mode ) 8K50F3E ( Narrow mode )
Frequency resolution 5 , 8.33 , 10 , 12.5 , 15 , 20 , 25 , 30 , 50 kHz
Number of memory Channels Antenna impedance Power requirement 13.8V DC +/-15% ( 11.7 - 15.8 V ) Ground method Negative ground Current drain Receive
Transmit Operating temperature Frequency stability Dimensions 142 ( w ) x 40 ( h ) x 174 ( d ) mm
Weight
136.000 - 173.995MHz ( RX, TX )
144.000 - 145.995MHz ( RX, TX )
50ohm unbalanced
0.6 A (max.) 0.4 A ( Squelched ) Approx. 12.0 A max.
-10 °C - 60°C
+/- 5ppm
( 142 x 40 x 188 mm for projection included )
Approx. 1.0 Kg
350.000 ~ 511.995MHz ( RX )
400.000 ~ 489.995MHz ( TX )
430.000 - 439.995MHz ( RX, TX)
100
+/- 2.5 ppm
■ Transmitter
Output power Hi
Mid Low
Modulation system Maximum Frequency
deviation Spurious emission Adjacent channel power
Noise and hum ratio Microphone impedance 2kohm
■ Receiver
Sensitivity -14 dBu for 12 dB SINAD
Receiver circuit
Intermediate frequency Squelch sensitivity Adjacent channel selectivity Inter-modulation rejection ratio Spurious and image rejection
ratio
Audio output power
50 W 35 W 20 W 20 W
Approx. 5 W Approx. 5 W
Variable reactance frequency modulation
+/- 5kHz ( Wide mode ) +/- 2.5kHz ( Narrow mode )
-60 dB
- 60 dB
- 40 dB ( Wide mode ) - 34 dB ( Narrow mode )
Double conversion super-heterodyne
1st 21.7 MHz 2nd 450kHz
- 65 dB ( Wide mode ) - 55 dB ( Narrow mode )
2.0 W ( 8ohm , 10 %THD)
1st 30.85 MHz 2nd 455kHz
- 18 dBu
60 dB
70 dB
! NOTE : All specifications are subject to change without notice or obligation.
2
C IR C U I T D E S C R I P T IO N
1) Receiver System DR-135
The receiver system is a double super-heterodyne system with a 21.7MHz first IF and a 450kHz second IF.
1. Front End
2. IF Circuit
3. Demodulation Circuit
The received signal at any frequency in the 136.000MHz to 173.995MHz
range is passed through the low-pass filter (L116, L115, L114, L113, C204, C203, C202, C216 and C215) and tuning circuit {L105, L104 and D105, D104), and amplified by the RF amplifier (Q107). The signal from Q107 is
then passed through the tuning circuit (L103, L102, and variable capacitor
D103, D102) and converted into 21.7MHz by the mixer (Q106). The tuning
circuit, which consists of L105, L104, variable capacitor D105 and D104,
L103, L102, variable capacitor D103 and D102, is controlled by the tracking voltage from the VCO. The local signal from the VCO is passed through the buffer (Q145), and supplied to the source of the mixer (Q106). The radio uses the lower side of the super-heterodyne system.
The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XF102, XF101) selects
21.7 MHz frequency from the results and eliminates the signal of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected frequency.
After the signal is amplified by the first IF amplifier (Q105), it is input to pin16 of the demodulator IC (IC108). The second local signal of 21.25MHz {shared with PLL IC reference oscillation), which is oscillated the external oscillator X601 and IC601, is input through pin 1 of IC108. Then, these two signals are mixed by the internal mixer in IC108 and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL102 or FL101), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pin
5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC 108, and output as an audio signal through pin 9.
4. Audio Circuit
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier (1C120:A), and switched by the signal switch IC (IC111) and then input it to the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the
de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the AF amplifier (IC120:B). The signal is then input to volume (VR1). The adjusted signal is sent to the audio power amplifier (IC117) through the pin 1 to drive the speaker.
3
5. Squelch Circuit
The detected output which is outputted from pin 9 of IC108 is inputted to pin 8 of IC108 after it was been amplified IC120:Aand it is outputted from pin 7 after the noise component was been eliminated from the composed band pass filter in the built in amplifier of the IC, then the signal is rectified by the internal diode in IC108 to convert into DC component. The adjusted
voltage level at VR101 is delivered to the comparator of the CPU. The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes “L” level, AF control signal is begin controlled and sounds is outputted from speaker.
6. WIDE/NARROW Switching circuit secor|d IF 450kHz signal which passes through filter FL101 (wide)
and FL102 (narrow) during narrow, changes its width using the width control switching D116 and D115.
2) Transmitter System DR-135
1. Modulator Circuit
The audio signal is converted to an electrical signal by the microphone, and input it to the microphone amplifier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mic-volume by means of mic-gain adjust VR106. IC114:D and C consists of two operational amplifiers; one amplifier (pin 12,13 and 14) is composed of pre-emphasis and I DC circuit and the other (pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) {9600 bps packet signal input switch) and input to the cathode of the
variable capacitor of the VCO, to change the electric capacity in the
oscillation circuit. This produces the frequency modulation.
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the younger amplifier {Q115), and input to the final power module (IC110). The signal is then amplified by the final power module (IC110) and led to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116, C215, C216, C202, C203 and C204), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by D111, converted to DC. The detection voltage is passed through the APC circuit (!C114:A, IC114:B), then it controls the APC voltage supplied to final power module IC110 to fix the transmission power.
3) PLL Synthesizer Circuit DR-135
1.PLL
The dividing ratio is obtained by sending data from CPU (IC1) to pin 10 and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q135) and input to pin 8 of IC116. Each programmable divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz.
4
2. Reference Frequency Circuit "^e re^erence frequency appropriate for the channel steps is obtained by
dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5,10,15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used.
3. Phase Comparator Circuit
4. PLL Loop Filter Circuit
5. VCO Circuit
6. VCO Shift Circuit
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase comparator In the IC116 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in IC116.
If a phase difference is found in the phase comparison between the reference frequency and the VCO output frequency, the charge pump output (pin 5) of IC116 generates a pulse signal, which is converted DC voltage by the PLL loop filter and input to the input to the variable capacitor of the VCO unit for oscillation frequency control.
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D122 and D123). This change
the oscillation frequency, which is amplified by the VCO buffer (Q134, Q145) and output from the VCO area.
During transmission or the AIR band Reception (118-136 MHz), the VCO shift circuit turns ON Q138, change control the capacitance of L123 and safely oscillates the VCO by means of H signal from pin 42 of 1C1.
4) Receiver System DR- 435
The receiver system is a double super-heterodyne system with a 30.85MHz first IF and a 455kHz second IF.
1. Front End
2. IF Circuit
The received signal at any frequency in the 430.000MHz to 439.995MHz
range is passed through the low-pass filter ( L115, L114, L116, C204,
C203, C202, C216 and C215) and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through the BPF circuit (L103, L102) and converted into 30.85MHz by the mixer (Q106). The local signal from the VCO is passed through the buffer (Q134, Q145), and supplied to the source of the mixer (Q106). The radio uses the tower side of the super-heterodyne system.
The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XF101) selects 30.85 MHz frequency from the results and eliminates the signal of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected frequency.
5
3. Demodulation Circuit
After the signal is amplified by the first IF amplifier (Q105), it is input to
pin16 of the demodulator IC (IC108). The second local signal of
30.395MHz (Crystal oscillator) is input through pin 1 of IC108. Then, these
two signals are mixed by the internal mixer in IC108 and the result is
converted into the second IF signal with a frequency of 455kHz. The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL101 or FL102), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pin
5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC 108, and output as an audio signal through pin 9.
4. Audio Circuit
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier
(IC120:A), and switched by the signal switch IC (IC111) and then input it to
the de-emphasis circuit. And is compensated to the audio frequency characteristics in the
de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and
amplified by the AF amplifier (IC120:B). The signal is then input to volume
(VR1). The adjusted signal is sent to the audio power amplifier (IC117) through the pin 1 to drive the speaker.
5. Squelch Circuit
The detected output which is outputted from pin 9 of IC108 is inputted to
pin 8 of IC108 after it was been amplified IC120:A and it is outputted from
pin 7 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the IC, then the signal is rectified
by the internal diode in IC108 to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the CPU. The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes “L” level, AF control signal is begin controlled and sounds is outputted from speaker.
6. WIDE/NARROW Switchina circuit seconc* ^ 455kHz signal which passes through filter FL101 (wide)
and FL102 (narrow) during narrow, changes its width using the width control switching D116 and D115.
5) Transmitter System DR- 435
1. Modulator Circuit
6
The audio signal is converted to an electrical signal by the microphone, and input it to the microphone amplifier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mic-volume by means of mic-gain adjust VR106.
IC114:D and C consists of two operational amplifiers; one amplifier (pin
12,13 and 14) is composed of pre-emphasis and IDC circuit and the other (pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the
variable capacitor of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation.
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the drive
amplifier (Q138) and younger amplifier (Q115), and input to the final
power module (IC110). The signal is then amplified by the final power
module (IC110) and led to the antenna switch (D110) and low-pass filter
(L116, L114, L115, C215, C216, C202, C203 and C204), where unwanted
high harmonic waves are reduced as needed, and the resulting signal is
supplied to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:A, IC114:B), then it controls the APC voltage supplied to the final power module IC110tofix the transmission power.
6) PLL Synthesizer Circuit DR- 435
1. PLL
2. Reference Frequency Circuit "^e reference frequency appropriate for the channel steps is obtained by
The dividing ratio is obtained by sending data from CPU (IC1) to pin 10 and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q135) and input to pin 8 of IC116, Each programmable divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz.
dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used.
3. Phase Comparator Circuit
4. PLL Loop Filter Circuit
5. VCO Circuit
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase comparator in the IC116 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in IC116.
If a phase difference is found in the phase comparison between the reference frequency and the VCO output frequency, the charge pump output (pin 5) of IC116 generates a pulse signal, which is converted DC
voltage by the PLL (oop filter and input to the input to the variable capacitor of the VCO unit for oscillation frequency control.
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D122 and D123). This
change the oscillation frequency, which is amplified by the VCO buffer (Q134, Q145) and output from the VCO unit.
7
7) CPU and Peripheral Circuits
1. LCD Display Circuit
2. Reset and Backup
3. S (Signal) Meter Circuit
4. DTMF Encoder
5. Tone Encoder
The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency is 64 Hz.
When the power from the DC cable increases from Circuits 0 V to 2.5 V or more, “H” level reset signal is output from the reset IC (IC4) to pin 33 of the CPU (IC1), causing the CPU to reset. The reset signal , however, waits at 100, and dose not enter the CPU until the CPU clock (X1) has stabilized.
The DC potential of IF IC is input to pin 1 of the CPU (IC1), converted from an analog to a digital signal, and displayed as the S-meter signal on the LCD.
The CPU (IC1) is equipped with an internal DTMF encoder. The DTMF
signal is output from pin 10, through R35, R34 and R261 (for level adjustment), and then through the microphone amplifier (IC114:A), and is sent to the variable capacitor of the VCO for modulation. At the same time,
the monitoring tone passes through the AF circuit and is output from the speaker.
The CPU (IC1) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor (D122 and D123) of the VCO for modulation.
6. DCS Encoder
The CPU (IC1) is equipped with an internal DCS code encoder. The code
(023 to 754) is output from pin 9 of CPU to the voltage control pin of
VCTCXO (X102) of the PLL reference oscillator. When DCS is ON, DCS
MUTE circuit (Q126-ON, Q133-ON, Q132-OFF) works. The modulation
activates in X102 side only.
7. CTCSS, DCS Decoder
The voice band of the AF output signal from pin 1 of IC120:A is cut by sharp active filter IC104:A, B and C (VCVS) and amplified, then led to pin 4 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match.
During DCS, Q108 is ON, C419 is working and cut off frequency is
lowered.
8) Power Supply Circuit
When power supply is ON, there is a “L” signal being inputted to pin 39 (PSW) of CPU which enables the CPU to work. Then, “H” signal is outputted from pin 41 (C5C) of CPU and drives ON the power supply switch control Q8 and Q7 which turns the 5VS ON. 5VS turns ON the PLL IC (IC116), main power supply switch Q127 and Q122, AF POWER IC117 and the 8V of AVR (IC115). During reception, pin 29 (R5) of CPU outputs “H” level, Q124 is ON, and the reception circuits supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs “L” level which is
reverse by Q11 so that the output in Q128 will be “H” level, Q123 is ON, and the transmission circuit is supplied by
8 V. Or, in the case when the condition of PLL is UNLOCK, “H” level is outputted from pin 14 of PLL IC, UNLOCK switch Q129 is ON, transmission switch Q128 is OFF which makes the transmission to stop.
8
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No. Terminal
1 2 P66/AN6 SQL I 3 P65/AN5 BP5 I 4 5 P63/SCLK22/AN3 BP1 I 6 7 8 P 60/S IN 2/AN 0 RE2 I 9
10
11 12 P54/CNTR0 13 P53/RTP1 BP4 I/O Band plan 4 14 15
16 17 P47/SRDY1 TSTB 18 P46/SCLK1 STB 19
20
.21 P43/(p/TOUT BEEP
22 P42/INT2 SEC I 23 P41/INT1 RE1 I 24
25 26 27 28 P74 T5 29 30 31 32 P70/INT0 BU 33 RESET RESET 34 35 36 XIN 37 38 VSS 39 P27 PSW I
40 P26 SDA o
41 P25 CSC 0 42 P24 AIR 0 43 44 45 46 P20 47 P17 SW4 I 48 P16 SW3 I 49 50
P67/AN7
P64/AN4
P62/SCLK21/AN2
P61/SOUT2/AN1
P57/ADT/DA2
P56/DA1
P55/CNTR1
P52/RTP0 P51/PWM1 CLK P5O/PWM0
P45/TXD UTX
P44/RXD RTX
P40 P77 P76 P75
P73 P72 P71
XCIN
XCOUT
XOUT
P23 P22 P21
P15/SEG39 P14/SEG38
Signal I/O Description
SMT I
TIN I
BP2 I
DCSW 0
TOUT 0 CTCSS tone output / DCS tone output DOUT 0 DTMF output
SCL 0 Serial clock for EEPROM
TBST 0 Tone burst output
MUTE I/O
O
DATA I/O Serial data output for PLL / PLL unlock signal input
I/O Trunking board detection / Strobe signal to trunking board
0 Strobe for PLL IC 0 UART data transmission output
I/O Beep tone / Band plan 3
PTT I
SSTB
W/N
R5
SQC
Xcin -
Xcout
Xin - Xout GND
LOW
EXP SW6 SW5
SW2 I SW1 I
o Security mode
0 Wide Narrow SW 0
o RX power ON / OFF output o SQL O N/ OFF
0 Tx low power 0
S-meter input Noise level input for squelch Band plan 5 CTCSS tone input / DCS code input Band plan 1 Band plan 2 DCS signal mute Rotary encoder input
Microphone mute / Security alarm SW Serial clock output for PLL
I UART data reception output
Security voltage input Rotary encoder input
PTT input
TX power ON / OFF output
I Backup signal detection input I Reset input
-
- -
Main clock input
-
Main clock output
-
CPU GND
Power switch input Serial data for EEPROM C5V power ON / OFF output Tx middle power
Trunking / Packet data SW
I Key sw 6 (SQL) I Key sw 5 (CALL)
Key sw 4 (TSQ) Key sw 3 (MHz) Key sw 2 (V/M) Key sw 1 (FUNC)
10
No. Terminal Signal
51
52 P 12/S EG 36
53 P11/SEG35 54 55
56 57 P05/SEG31 S31 58 P04/SEG30 S30 0 59 60 61 62 63 64 65 66 P34/SEG22 67 P33/SEG21 68 P32/SEG20 S20 0 69 70 P30/SEG18 S18 0 71 SEG17 S17 0 72 SEG16 S16 0 73 SEG15 S15 0
74 SEG14 S14 0 75 SEG13 S13 0
76
77 78 SEG10 S10 0 79 SEG9 S9 80 SEG8 81 82 83 SEG5 S5 0 84 SEG4 S4 0 85 SEG3 S3 86 SEG2 S2 0 87 88 SEGO SO o 89 VCC 90 VREF Vref
91 AVSS Avss
92 COM3 COM3 o 93 COM2 COM2 0 94 COM1 COM1 o
95 COMO COMO o 96 VL3 VL3 97 VL2 VL2 98 C2 I - - 99 C1 C1
100 VL1 VL1
P13/SEG37 DOWN I
P10/SEG34 P07/SEG33 P06/SEG32
P03ÍSEG 2Q
P02/SEG28 P01/SEG27 POO/SEG26 P37/SEG25 P36/SEG24
P35/SEG23
P31/SEG19
SEG12 S12 0
SEG11 S11
SEG7 S7 o SEG6 S6
SEG1 S1
UP S33 0 S32 0
S29
S28 S27 0
S26
S25 0
S24 S23 S22 0 S21
S19
S8
VDD -
I/O
I
0
o 0
0
0 0
0
0
0
o 0
o
o
0
-
-
-
-
- I
Description
Mic down input
Mic up input
LCD segment signal
CPU power terminal AD converter power supply AD converter GND
LCD COM3 output
LCD COM2 output
LCD COM1 output
LCD COMO output
LCD power supply
LCD power supply
-
LCD power supply
I
SEMICONDUCTOR DATA
1) NJM7808FA (XA0102)
8V (1A) Voltage Regulator
1. INPUT
2. COMMON
3. OUTPUT
1 2 3
2) TC4S66F (XA0115)
Bilateral Switch
5 4
b
_____
a
C 9
b ti b
1 2 3
1. IN /OUT
2. OUT/IN
3. VSS
4. CONT
5. VDD
3) AN8010M (XA0119)
10V (50mA) Voltage Regulator
i i
•< o
1. OUTPUT
2. COMMON
3. INPUT
4) TC4W53FU (XA0348)
Multiplexer / De-multiplexer
1. COMMON
2. INH
3. VEE
4. VSS
5. A
6. ch 1
o
T O T
12 3 4
7. chO
8. VDD
5
n
£
e
□ □ ti
1 2 3
CONT Function (IN-OUT)
L Disconnect (Hi Z)
H Connect (290ohm typ.)
Control input
INH A
L L L H ch 1
H
Don’t care
*
ON channel
chO
NONE
12
5) TA31136FN (XA0404)
Narrow Band FM IF IC
16 15 14 13 12 11 10 9
1. OSC IN
2. OSC OUT
3. MIX OUT
4. Vcc
5. IF IN
6. DEC
7. FILOUT
8. FILIN
9. AF OUT
10. QUAD
11. IF OUT
12. RSSI
13. N-DET
14. N-REC
15. GND
16. MIX IN
6) LA4425A (XA0410)
5W Audio Power Amplifier
ö .
LA4425
* **
m o m
1 2 3 4 5
1. Input
2. Small signal GND
3. Large signal GND
4. Output
5. Vcc
Test C ircuit
13
7) BR24L32FJ (XA0604Z)
32K-Bit EEPROM
8 7 6 5
-ELELfLEL
L3 2
Q * * * * *
m i
2. A1
3.A2
4. Vss
5. SDA
6. SCL
7. WP
8. Vcc
12 3 4
8) S-80845ALMP (XA0620)
4.5V Voltage Detector
5
B 6 6 *
f l
4
1.GND
2. Vin
3. Vout
4. NC
5. NC
1 2 3
9) S-816A50AMC (XA0925)
Name Function
A0...A2 User Configurable Chip Select Vss Ground SDA Serial Address / Data / I/O SCL Serial Clock WP
Vcc +2.5 - 6.0V Power Supply
Write Protect Input
External Transistor Type 5V Voltage Regulator with On/Off Function
5
B A Z *
b b b
4
R
1. EXT
2. Vss
3. ON/OFF
4. Vin
5. Vout
1 2 3
10) NJM78M05DL1A (XA0947)
5V (500mA) Voltage Regulator
I
-----------
H
1. Input
2. GND
3. Output
14
U
2
-
—
11) LM2904PWR (XA1103)
Dual Operational Amplifiers
8 7 6 5
1. Output A
2. Inverting Input A
3. Non-inverting Input A
4. GND
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Vcc
12 3 4
12) LM2902PWR (XA1106)
Quad Operational Amplifiers
10 9 8
1. Output A
2. Inverting Input A
3. Non-inverting Input A
4. Vcc
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Output C
1 in I i t
2 3 4 5 6 7
9. Inverting Input C
10. Non-inverting Input C
11. GND
12. Non-inverting Input D
13. Inverting Input D
14. Output D
13) MB15E07SR (XA1107)
PLL Synthesizer
16 1 5 1 4 13 1 2 1 1 10 9
HRHRyy
E 0 7 S R
1 2 3 4 5 6 7 8
OSC IN
PS
LE
Data
Clock
Xfin
fin
Reference
Oscillator
Intermittent
mode control
(power saye)
1—bit
control latch
Prescaler
>
32/33
>
64/65
Binary 14-bit reference counter
14-bit latch
Sff
1.0S CIN 9. Clock
2. N. C. 10. Data
3. Vp 11. LE
4. Vcc 12. PS
5. Do 13. N. C.
6. GND 14. LD/tout
7. Xfin 15. N.C.
8. fin 16. N.C.
Sff FC
19-bit shift register
7-bit latch
Binaly 7-bit
swallow counter
11-bit latch
Binary 11-bit
programmable
4-bit
counter
LDS CS latch
fr
Phase
comparator
Lock
detector
LD/fr/fp
selector
Charge pump
fp
LD/fout
Vp
Do
VCC
GND
Parameter Power supply voltage Power supply current LPF supply voltage Local oscillator input level Local oscillator input
frequency Xin input level Vxin Xin input frequency Fxin
16
Symbo
1
Vcc
Icc
Vp
Vfin
fin
( Vcc = 2.7 to 5.0V, Ta = -40°C to +85oC )
Condition Min.
-
2500MHz
Vcc=Vp=3.75V
-
100MHz to 300MHz
300MHz to 2500MHz
-
-
-
Typ. Max. Unit
2.7 3.75
5.0
8.0
Vcc
-6
-15
-
5.5 +2 +2
100 2500
0.5 3
Vcc
40
V
mA
V
dBm
MHz
Vp-p
MHz
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