ALESS AL1402 Datasheet
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General Description
The AL1402 OptoRec interface is designed
to decode the ADAT
and produce four stereo pairs of audio
data. Alesis ADAT
5,297,181.
Use of this product requires a license
agreement between manufacturer and
Alesis Studio Electronics. Details and
agreement information are available upon
request from Alesis Semiconductor or
Alesis Studio Electronics.
â
optical data stream
â
U.S. patent number
GND
Features
G
Compatible with ADATâType I and II
formats
G
4stereopairsasoutputsusing
standard ADC formats
G
4 user bit outputs to receive time-code,
MIDI data, etc.
G
Internal PLL generates required clocks
from optical data.
G
Word Clock input to synchronize
outputstouser’ssystem.
Applications
G
Receive information from ADAT
compatible devices.
VDD
â
MODE0
FMT0
FMT1
MODE1
OPDIGIN
SVCO
WDCLK
BCLK
OUT 1/2
OUT 3/4
OUT 5/6 OUT 7/8
Figure A. 24 pin SOIC
Alesis Semiconductor
DS1402-0702 12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
LINMODE
MUTE
ERROR
HOLDERR
OPDIGTHRU
DVCO
USER3
USER2
USER1
USER0
Table 1 Electrical Characteristics and Operating Conditions
Symbol Description Min Typ Max Units
Recommended Operating Conditions
V
DD
IDDMaster Supply Current, Master - 7.7 - mA
IDDSlave Supply Current, Slave - 5.4 - mA
GND Ground - 0.0 - V
Fs Sample rate 30 48 55 kHz
Temp
Supply Voltage 4.5 5.0 5.5 V
Temperature 0 25 70
°C
Inputs (WDCLK, FMT, OPDIGIN, MODE, LINMODE, MUTE, HOLDERR)
V
IH
V
IL
I
IH
I
IL
C
IN
Logical “1” input voltage 0.75 V
DD
Logical “0” input voltage - - 0.25 V
--V
DD
V
Logical “1” input current - - 1 uA
Logical “0” input current - - 1 uA
Logic Input Capacitance - 5 - pF
DD
DD
Outputs (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR)
V
OH
V
OL
I
OH
I
OL
Logical “1” output voltage 0.9 V
DD
Logical “0” output voltage - - 0.1 V
--V
DD
V
Logical “1” output current - - -8 mA
Logical “0” output current - - 8 mA
DD
DD
Outputs (OUT, USER)
V
OH
V
OL
I
OH
I
OL
Logical “1” output voltage 0.9 V
DD
Logical “0” output voltage - - 0.1 V
--V
DD
V
Logical “1” output current - - -2 mA
Logical “0” output current - - 2 mA
DD
DD
Table 2 Pin Descriptions
Pin # Name Pin
Type
1GND PowerGroundpin
2 MODE0 Input Mode select
3 FMT0 Input Format select
4 FMT1 Input Format select
5 MODE1 Input Mode select
6 OPDIGIN Input Input from optical receiver
7SVCO Output
8 WDCLK I/O Input or output word clock, see Table 4, Modes (nominal 48KHz, Fs)
9 BCLK Output Bit clock (nominal 3.072MHz, 64 x Fs)
10 OUT 1/2 Output Channels 1 and 2 data output
11 OUT 3/4 Output Channels 3 and 4 data output
12 OUT 5/6 Output Channels 5 and 6 data output
13 OUT 7/8 Output Channels 7 and 8 data output
14 USER0 Output USER0 data bit output. Used to receive timecode
15 USER1 Output USER1 data bit output. Used to receive MIDI data.
16 USER2 Output USER2 data bit output. Reserved.
17 USER3 Output USER3 data bit output. Reserved.
18 DVCO Output Recovered clock from data stream(nominal 12.288MHz, 256 x Fs)
19 OPDIGTHRU Output OPDIGIN is regenerated and clocked out on this pin to allow daisy-chaining
20 HOLDERR Input
21 ERROR Output
22 MUTE Input If high, mutes outputs
23 LINMODE Input Tie high
24 V
DD
Power +5V power pin
Derived clock from WDCLK in slave mode; derived from DVCO in Master mode
(nominal 12.288MHz, 256x Fs)
If high, the ERROR pin stays high until th e cause of the error is removed AND
the HOLDERR pin goes low.
Indicates lack of input or failure to synchronize to data stream, mutes data
outputs but not clock outputs
Description
Alesis Semiconductor
DS1402-0702 12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
-2-
Master and Slave Modes
Use
Master Mode:
All outputs are derived from the input
optical format data stream on the OPDIGIN
(pin 6). WDCLK is an output.
Slave Mode:
DAC outputs, USER outputs, BCLK and
SVCO outputs are synchronized to WDCLK,
which is an input.
In Slave mode, WDCLK may be at an
arbitrary phase with respect to the incoming
samplesofOPDIGIN,butifthefrequencies
aren’t identical samples will be dropped,
repeated, or garbled. Generally, identical
frequencies are achieved by either: using
DVCO (pin 18) as the source from which
WDCLK is generated, or creating OPDIGIN
from a source synchronized to WDCLK.
The AL1402 OptoRec interface has been
designed for ease of use and flexibility in
systems designed to interface to the ADAT
â
protocol. It supports both left and right
justified data formats for ease of integration
into existing devices as well as new devices.
These formats allow it to operate in parallel
with many standard ADC’s.
The designer uses the FMT0, FMT1, MODE0
and MODE1 pins to select the desired
format and mode.
The format pins are summarized in Table 3,
Formats. The A L1402 provides support for
â
both the ADAT
the ADAT
â
Type I format (16-bit) and
Type II format (20-bit). Data
output is 24 bit. Data input lengths up to
24 bits is supported.
â
USER0isusedtoreceivetheADAT
format
32-bit timcode; USER1 is used to receive
MIDI data (if the source device supports
these features). USER2 and USER3 are
reservedandshouldnotbeused.
Table 3 Formats
FMT1 FMT0 Format
0 0 OUT data is right justified, B CLK falls on changing WDCLK
0 1 OUT data is left justified, BCLK rises on changing WDCLK
1 0 Chip Reset
1 1 Gated BLCK, BCLK rises on changing WDCLK
Table 4 Modes
MODE1 MODE0 Mode
0 0 Master mode, WDCLK is an output
01
1 0 Reserved
1 1 Reserved
DS1402-0702 12555 Jefferson Blvd., Suite 285
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
Slave mode, WDCLK is an input. WDCLK MUST be derived from the same clock
supplying the source
Alesis Semiconductor
Los Angeles, CA 90066
-3-
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