ASAHI KASEI [AKD4562]
AKD4562
Evaluation board Rev.A for AK4562
GENERAL DESCRIPTION
AKD4562 is an evaluation board for the portable digital audio 20bit A/D and D/A converter, AK4562. The
AKD4562 can evaluate A/D converter D/A converter separately in addition to loopback mode (A/D →
D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly. The
AKD4562 has the interface with AKM’s wave generator using ROM data and AKM’s ADC evaluation
boards. Therefore, it’s easy to evaluate the D/A section. The AKD4562 also has the digital audio interface
and can achieve the interface with digital audio systems via opt-connector.
n Ordering guide
AKD4562 --- Evaluation board for AK4562
(Cable for connecting with printer port of IBM-AT,
compatible PC and control software are packed with this.)
FUNCTION
• Compatible with 2 types of interface
- Direct interface with AKM’s A/D & D/A converter evaluation boards
- DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
GND
LIN1/2
RIN1/2
VTVA
CS8412
(DIR)
Opt In
AK4562
LOUT1/2
ROUT1/2
AK4353
(DIT)
Opt Out
A/D, D/A Data
Control
Data
10pin Header
Figure 1. AKD4562 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Clock
Generator
ROM Data
10pin Header
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ASAHI KASEI [AKD4562]
1. Evaluation Board Manual
n Input / Output circuits & Set-up jumper pin for Input / Output circuits
(1) LINE Block
(a) LIN1,2/RIN1,2 Input circuits
J2
LIN
R36
560
C38
10u
+
JP15
LIN
LIN1
LIN1
LIN2
LIN2
J4
RIN
R38
560
C41
10u
+
JP18
RIN
RIN1
RIN1
RIN2
RIN2
Figure 2. LIN1,2/RIN1,2 Input circuits
1. Analog signal is input to LIN1 and RIN1 pins via J2 and J4 connectors.
JP15
LIN
LIN1
LIN2
JP18
RIN
RIN1
RIN2
2. Analog signal is input to LIN2 and RIN2 pins via J2 and J4 connectors.
JP15
LIN
LIN1
LIN2
JP18
RIN
RIN1
RIN2
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ASAHI KASEI [AKD4562]
(b) LOUT1/ROUT1 and OPGAL/OPGAR Selection circuits
R34
LOUT1
OPGAL
ROUT1
OPGAR
LOUT1
OPGL
ROUT1
OPGR
+
+
C39
1u
JP17
OPGL
C43
1u
JP20
OPGR
+
C37
22u
+
C42
22u
+
C40
1u
+
C44
1u
R35
10k
R40
10k
220
R39
220
JP16
LIO
JP19
RIO
OPGL LOUT1OPGR
R37
560
ROUT1
R41
560
J3
LOUT1
J5
ROUT1
Figure 3. LOUT1/ROUT1 and OPGAL/OPGAR Selection circuits
1. Analog signal is input to OPGAL and OPGAR pins via J3 and J5 connectors.
JP16
LIO
JP17
OPGL
OPGLLOUT1
OPGLLOUT1
JP19
RIO
OPGRROUT1
JP20
OPGR
OPGRROUT1
2. Analog signal is output to LOUT1 and ROUT1 pins via J3 and J5 connectors.
JP16
LIO
JP17
OPGL
OPGLLOUT1
OPGLLOUT1
JP19
RIO
OPGRROUT1
JP20
OPGR
OPGRROUT1
3. Analog signal is input to OPGAL and OPGAR pins via LOUT1 and ROUT1 pins.
JP16
LIO
JP17
OPGL
JP19
RIO
JP20
OPGR
OPGLLOUT1
OPGLLOUT1
OPGRROUT1
OPGRROUT1
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ASAHI KASEI [AKD4562]
(2) Other Jumper pins
1. JP1 (CSN) : Selection of CSN pin
SSB : SSB mode.
AKM : AKM mode.
2. JP2 (SSB) : Selection of SSB mode or AKM mode
OPEN : AKM mode.
SHORT : SSB mode.
3. JP3 (TST) : Selection of TEST pin
OPEN : Normal mode.
SHORT : Test mode.
* Always open.
4. JP4 (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT : Common. (The connector “DGND” can be open.) <default>
5. JP5 (VT) : D2V and VT
OPEN : Separated. <default>
SHORT : Common. (The connector “VT” can be open.)
6. JP9 (SDTO) : SDTO of AK4562
Always open. It can be short for only evaluation mode “7) ”.
7. JP10 (MODE) : Setting mode of CS8412
OPEN : I
2
S compatible mode.
SHORT : 16 bit LSB justified.
* AKM assumes no responsibility for the trouble when using the above circuit examples.
n Operation sequence
1) Set up the power supply lines.
[VA] (orange) = 2.2 ∼ 3.0V : for VA of AK4562 (typ. 2.5V)
[VT] (orange) = 1.8 ∼ 3.0V : for VT of AK4562 (typ. 2.5V)
[D2V] (orange) = 1.8 ∼ 3.0V : for 74LVC541 (typ. 2.5V)
[D5V] (red) = 3.6 ∼ 5.0V : for logic (typ. 5.0V)
[AGND] (black) = 0V : for analog ground
[DGND] (black) = 0V : for logic ground
Each supply line should be distributed from the power supply unit.
VT and D2V must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
Note : This evaluation board corresponds to I
2
S compatible mode for evaluation of A/D.
3) Power on.
The AK4562 and AK4353 should be reset once bringing SW1, 2 “L” upon power-up.
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ASAHI KASEI [AKD4562]
JP13
R
R
n Evaluation mode
Applicable Evaluation Mode
1) Evaluation of loopback mode (default)
2) Evaluation of D/A using ideal sine wave generated by ROM data
3) Evaluation of D/A using A/D converted data
4) Evaluation of D/A using DIR (Optical Link)
5) Evaluation of A/D using D/A converted data
6) Evaluation of A/D using DIT (Optical Link)
7) All interface signals including master clock are fed externally.
6)
5)
AKD43XX
D/A Board
AKD4562
PORT2
10pin-Header
1)
1) Evaluation of loopback mode. <default>
Nothing should be connected to PORT3 and PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). This mode corresponds to only I
compatible mode.
ADC
JP7
LRCK
DI
JP6
X_BCLK
64fs32fs
JP8
BCLK
PORT4
DIR
DIRADC
PORT3
10pin-Header
3)
2)
JP1 1
SDTI
ADC
PORT1
DI
DIT
CD Player
4)
AKD53XX
A/D Board
ROM Board
2
S
JP12
DIR
CLK
JP14
XTE
GNDVD
DIR
EXT
XTL
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ASAHI KASEI [AKD4562]
JP13
R
R
JP13
R
R
JP13
R
R
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data.
Digital signals generated by AKD43XX are used. PORT3 is used for the interface with AKD43XX. Master
clock is sent from AKD4562 to AKD43XX and BCLK, LRCK, SDTI are sent from AKD43XX to
AKD4562. Nothing should be connected to PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP1 1
SDTI
JP12
DIR
CLK
JP14
XTE
64fs32fs
ADC
DI
3) Evaluation of D/A using A/D converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3. Nothing should be connected to PORT4. In case of using
external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP6
X_BCLK
64fs32fs
ADC
JP7
LRCK
DI
JP8
BCLK
4) Evaluation of D/A using DIR. (Optical link)
PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3. DIR (CS8412) corresponds to only I
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
DIRADC
ADC
DI
JP1 1
SDTI
DIRADC
ADC
DI
2
S compatible mode or 16 bit LSB justified.
JP1 1
SDTI
JP12
DIR
JP12
DIR
GNDVD
DIR
EXT
XTL
JP14
CLK
XTE
GNDVD
DIR
EXT
XTL
JP14
CLK
XTE
64fs32fs
ADC
DI
DIRADC
ADC
DI
GNDVD
DIR
EXT
XTL
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ASAHI KASEI [AKD4562]
JP13
R
R
JP13
R
R
JP13
R
R
5) Evaluation of A/D using D/A converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3. Nothing should be connected to PORT4.
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP1 1
SDTI
JP12
DIR
CLK
JP14
XTE
64fs32fs
6) Evaluation of A/D using DIT. (Optical link)
PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through
optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards on the
digital-amplifier which equips DIR input. Nothing should be connected PORT3 and PORT4. In case of
using external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). DIT
(AK4353) corresponds to only I
JP6
X_BCLK
64fs32fs
7) All interfacing signals (MCLK, BCLK, LRCK) are fed from the external circuit through PORT3.
PORT3 is used. JP7, 8, 11 and 13 should be open.
JP6
X_BCLK
ADC
ADC
DI
JP7
LRCK
DI
JP7
LRCK
DIRADC
2
S compatible mode.
JP8
BCLK
DIRADC
JP8
BCLK
ADC
ADC
JP1 1
SDTI
JP1 1
SDTI
DI
DI
JP12
DIR
JP12
DIR
GNDVD
DIR
EXT
CLK
GNDVD
DIR
EXT
CLK
XTL
XTL
JP14
XTE
JP14
XTE
64fs32fs
ADC
DI
DIRADC
ADC
DI
GNDVD
DIR
EXT
XTL
n The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power down of AK4562. Keep “H” during normal operation.
[SW2] (DIT): Power down of AK4353. Keep “H” during normal operation.
n Indication for LED
[LED1] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to CS8412.
[LED2] (PREM): Indicate whether the input data of CS8412 is pre-emphasized or not.
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ASAHI KASEI [AKD4562]
n Serial Control
The AK4562 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(CTRL) with PC by 10 wire flat cable packed with the AKD4562.
Connect
PC
10 wire
flat cable
10pin
10pin Header
Connector
Figure 4. Connect of 10 wire flat cable
CCLK
CDTI
AKD4562
CSN
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ASAHI KASEI [AKD4562]
2. Control Software Manual
n Set-up of evaluation board and control software
1. Set up the AKD4562 according to previous term.
2. Connect IBM-AT compatible PC with AKD4562 by 10-line type flat cable (packed with AKD4562). Take care of the
direction of 10pin header. (This control software does not operate on Windows NT, therefore please operate it on
Windows95/98.)
3. Insert the floppy-disk labeled “AKD4562 Control Program ver 1.0” into the floppy-disk drive.
4. Access the floppy-disk drive and double-click the icon of “AKD4562.exe” to set up the control program. This
software corresponds to only AKM mode.
5. Then please evaluate according to the follows.
n Explanation of each buttons
1. [Port Setup] : Set up the printer port.
2. [Reset] : Initialize the register of AK4562.
3. [Function1] : Dialog to write data by keyboard operation.
4. [Function2] : Dialog to evaluate IPGA and OPGA.
5. [Write] : Dialog to write data by mouse operation.
Note : AK4353(DIT) is fixed to MCLK=256fs and I
AK4562’s ADC, it is necessary for AK4562 to set up MCLK=256fs and I
2
S compatible mode. Therefore, in the case of evaluation for
2
S compatible mode.
n Explanation of each dialog
1. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input register address in 2 figures of hexadecimal.
Data Box: Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4562, click “OK” button. If not, click “Cancel” button.
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