AKM AK6440BH, AK6420BH, AK6480BH Datasheet

ASAHI KASEI [AK6420B/40B/80B]

AK6420B / 40B / 80B

2K / 4K / 8Kbit Serial CMOS EEPROM

Features

ADVANCED CMOS EEPROM TECHNOLOGY

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Wide Vcc (1.8V ∼ 5.5V) operation

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AK6420B

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AK6440B
AK6480B

ONE CHIP MICROCOMPUTER INTERFACE

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LOW POWER CONSUMPTION

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2048 bits: 128 Õ 16 organization

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4096 bits: 256 Õ 16 organization

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8192 bits: 512 Õ 16 organization

- Interfac e with one chip micro computer's serial comm unication port directly

- 0.8

A Max (Standby mode)

µ

HIGH RELIABILITY

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-Endurance : 100K cycles

-Data Retention : 10 years

SPECIAL FEATURES

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- High speed operation ( f

=1MHz: Vcc=2.5V )

MAX

- Automatic write cycle time-out with auto-ERASE

- Automatic address increment (READ)

- Software and Hardware controlled write protection

IDEAL FOR LOW DENSITY DATA STORAGE

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- Low cost, space saving, 8-pin package (MSOP)

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ASAHI KASEI [AK6420B/40B/80B]

General Description

The AK6420B/40B/80B is a 2048/4096/8192bit, serial, read/write, non-volatile memory device fabricated using
an advanced CMOS E2PROM technology. The AK6420B has 2048bits of memory organized into 128
registers of 16 bits each. The AK6440B has 4096bits of memory organized into 256 registers of 16 bits each.
The AK6480B has 8192bits of memory organized into 512 registers of 16 bits each. The AK6420B/40B/80B
can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is
integrated for high voltage generation that is used for write operation.
The AK6420B/40B/80B can connect to the serial communication port of popular one chip microcomputer
directly (3 line negative clock synchronous interface). At write operation, AK6420B/40B/80B takes in the write
data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin
(SK). And at read operation, AK6420B/40B/80B takes out the read data from a register to data output pin
(DO) synchronously with falling edge of SK.
The AK6420B/40B/80B has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS (write
disable). Each instruction is organized by op-code block (8bits), address block (8bits) and data (8bits Õ 2).
When input level of SK pin is high level and input level of chip select (CS) pin is changed from high level to low
level, AK6420B/40B/80B can receive the instructions.
Special features of the AK6420B/40B/80B include : automatic write time-out with auto-ERASE, Ready/Busy
status signal output and ultra-low standby power mode when deselected (CS=high).

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Software and Hardware controlled write protection
The AK6420B/40B/80B has 2 (hardware and software) write protection functions.
After power on or after execution of WRDS (write disable) instruction, execution of WRITE instruction will be
disabled. This write protection condition continues until WREN instruction is executed or Vcc is removed from
the part.
Execution of READ instruction is independent of both WREN and WRDS instructions.
Reset pin should be low level when WRITE instruction is executed. When the Reset pin is high level, the
WRITE instruction is not executed.

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Ready/Busy status signal
The DO pin indicates the Busy status. When input level of SK pin is low level and input level of CS pin is
changed from high level to low level, the AK6420B/40B/80B is in the status output mode and the DO pin
indicates the Ready/Busy status. The Ready/ Busy status outputs on DO pin until CS pin is changed from low
level to high level, or first bit ("1") of op-code of next instruction is given to the part. Except when the device is
in the status output mode or outputs data, the DO pin is in the high impedance state.

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Ty pe of Products

Model Memory size Temp.Range Vcc Package
AK6420BH 2Kbits
AK6440BH 4Kbits
AK6480BH 8Kbits

-40°C∼85°C1.8V

-40°C∼85°C1.8V

-40°C∼85°C1.8V

∼

5.5V

∼

5.5V

∼

5.5V

8pin Plastic MSOP
8pin Plastic MSOP
8pin Plastic MSOP

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ASAHI KASEI [AK6420B/40B/80B]

Pin arrangement

Pin Name Function

CS Chip Select
SK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

RESET RESET Input

Vcc Power Supply

GND Ground

NC Not Connected

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ASAHI KASEI [AK6420B/40B/80B]

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Pin Description

CS (Chip Select)

When SK is high level and CS is changed from high level to low level, AK6420B/40B/80B can receive the
instructions. CS should be kept low level while receiving op-code, address and data and while outputting data.
If CS is changed to high level during the above period, AK6420B/40B/80B stops the instruction execution.
When SK is low and CS is changed from high level to low level, AK6420B/40B/80B will be in status output
mode. The CS need not be low level during the automatic write time-out period (BUS Y status).

SK (Serial Clock)
The SK clock pin is the synchronous clock input for input/output data. At write operation, AK6420B/40B/80B
takes in the write data from data input pin (DI) synchronously with rising edge of input pulse of serial clock pin
(SK). And at read operation, AK6420B/40B/80B takes out the read data to data output pin (DO)
synchronously with falling edge of SK. The SK clock is not needed during the automatic write time-out period
(BUSY status), the status output period and when the device isn't selected (CS = high level).

DI (Data Input)
The op-code, address and write data is input to the DI pin.

DO (Data Output)
The DO pin outputs the read data and status signal and will be high impedance except for this timing.

RESET (Reset)
The AK6420B/40B/80B stops executing the write instruction when the RESET pin is high level. The RESET
pin should be low level while the write instruction input period and the automatic write time-out period. If the
RESET pin is high level while the automatic write time-out period, the AK6420B/40B/80B stops execution of
internal programming and the device returns to ready status. In this case the word data of the specified
address will be incomplete. When inputting the new instruction after RESET, the CS pin should be set to high
level. The read, write enable and write disable instructions are not affected by RESET pin status.

Vcc (Power Supply)

GND (Ground)

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ASAHI KASEI [AK6420B/40B/80B]

Functional Description

The AK6420B/40B/80B has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS (write
disable). Each instruction is organized by op-code block (8bits), address block (8bits) and data (8bitsÕ2).
When input level of SK pin is high level and input level of chip select (CS) pin is changed from high level to low
level, AK6420B/40B/80B can receive the instructions.
When the instructions are executed consecutively, the CS pin should be brought to high level for a minimum of
250ns(Tcs) between consecutive instruction cycle.

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Instruction Set For 6420B

Instruction Op-Code Address Data
READ 1 0 1 0 1 0 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15 -D0
WRITE 1 0 1 0 0 1 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15 -D0
WREN 1 0 1 0 0 0 1 1
WRDS 1 0 1 0 0 0 0 0
( WRAL ) 1 0 1 0 1 1 1 1

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D15 -D0

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Instruction Set For 6440B

Instruction Op-Code Address Data
READ 1 0 1 0 1 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WRITE 1 0 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WREN 1 0 1 0 0 0 1 1
WRDS 1 0 1 0 0 0 0 0
( WRAL ) 1 0 1 0 1 1 1 1

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Instruction Set For 6480B

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D15 -D0

Instruction Op-Code Address Data
READ 1 0 1 0 1 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WRITE 1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WREN 1 0 1 0 0 0 1 1
WRDS 1 0 1 0 0 0 0 0
( WRAL ) 1 0 1 0 1 1 1 1

(Note) The WRAL instruction is used for factory function test only. User can't use this instruction .

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D15 -D0

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:don't care

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