The AK5392 is a 24bit, 128x oversampling 2ch A/D Converterfor professional digital audio systems. The modulator
in the AK5392 uses the new developed Enhanced Dual Bit architecture. This new architecture achieves the wider
dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. The
AK5392 performs 116dB dynamic range, so the device is suitable for professional studio equipments such as digital
mixer, digital VTR etc.
Features
Enhanced Dual Bit ADC
Sampling Rate: 1kHz∼54kHz
Full Differential Inputs
S/(N+D): 105dB
DR: 116dB
S/N: 116dB
High Performance Linear Phase Digital Anti-Alias filter
•
Passband: 0∼21.768kHz(@fs=48kHz)
•
Ripple: 0.001dB
•
Stopband: 110dB
Digital HPF & Offset Calibration for Offset Cancel
The following pin functions are changed from AK5391. AK5392 supports 24bit only.
Pin No.AK5391AK5392
2VREFL-GNDL
19SEL24HPFE
27VREFR-GNDR
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ASAHI KASEI[AK5392]
PIN/FUNCTION
No.Pin NameI/OFunction
1 VREFLO Lch Reference Voltage Pin, 3.75V
Normally connected to GNDL with a 10uF electrolytic capacitor and
a 0.1uF ceramic capacitor
2 GNDL- Lch Reference Ground Pin, 0V
3 VCOMLO Lch Common Voltage Pin, 2.5V
4 AINL+ I Lch Analog positive input Pin
5 AINL-I Lch Analog negative input Pin
6 ZCAL I Zero Calibration Control Pin
This pin controls the calibration reference signal.
"L":VCOML and VCOMR
"H":Analog Input Pins(AINL±,AINR±)
7 VD- Digital Power Supply Pin, 3.3V
8 DGND- Digital Ground Pin, 0V
9 CAL O Calibration Active Signal Pin
"H" means the offset calibration cycle is in progress. Offset calibration starts
when
RST
10
1112 SMODE2
SMODE1
13 LRCKI/O Left/Right Channel Select Clock Pin
I Reset Pin
When "L", Digital section is powered-down. Upon returning "H", an
offset calibration cycle is started. An offset cal ibration cycle should always
be initiated after power-up.
II Serial Interface Mode Select Pin
MSB first, 2's compliment.
SMODE2 SMODE1 MODE LRCK
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset
SCLK outputs a 128fs clock. SCLK stays "L" during reset.
15 SDATAO Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
16 FSYNCI/O Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA.
Master mode:
FSYNC outputs 2fs clock.
FSYNC stays "L" during reset.
17 CLKI Master Clock Input Pin
CMODE="H":384fs
CMODE="L":256fs
18 CMODEI Master Clock Select Pin
"L": CLK=256fs (12.288MHz @fs=48kHz)
"H": CLK=384fs (18.432MHz @fs=48kHz)
19 HPFEI High Pass Filter Enable Pin
"L": Disable
"H": Enable
20 TESTI T est Pin
Should be connected DGND.
21 BGND- Substrate Ground Pin, 0V
22 AGND- Analog Ground Pin, 0V
23 VA- Analog Supply Pin, 5V
24 AINR-I Rch Analog negative input Pin
25 AINR+I Rch Analog positive input Pin
26 VCOMRO Rch Common Voltage Pin, 2.5V
27 GNDR- Rch Reference Ground Pin, 0V
28 VREFRO Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10uF electrolytic capacitor and
a 0.1uF ceramic capacitor
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ASAHI KASEI[AK5392]
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1 )
ParameterSymbolminmaxUnits
Power Supplies: Analog
Digital
|BGND-DGND| (Note 2 )
Input Current, Any Pin Except SuppliesIIN Analog Input VoltageVINA-0.3VA+0.3V
Digital Input VoltageVIND-0.3VD+0.3V
Ambient Temperature (power applied)Ta-1070
Storage TemperatureTstg-65150
Note: 1 . All voltages with respect to ground.
2 . AGND and BGND mu st be same voltage.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
∆
GND
VA
VD
-0.3
-0.3
-
6.0
6.0
0.3
±
10
V
V
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1 )
ParameterSymbolmintypmaxUnits
Power Supplies: Analog
(Note 3 ) Digital
Notes:1 . All voltages with respect to ground.
3 . The power up sequence between VA and VD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data
sheet.