The AK4382 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4382 delivers a wide dynamic range while preserving linearit y for
improved THD+N performance. The AK4382 has full differential SCF outputs, removing the need for AC
coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word
length and 192kHz sampling rate make this part ideal for a wide range of applications including DVDAudio. The AK4382 is offered in a space saving 16pin TSSOP package.
FEATURES
o Sampling Rate Ranging from 8kHz to 192kHz
o 128 times Oversampling (Normal Speed Mode)
o 64 times Oversampling (Double Speed Mode)
o 32 times Oversampling (Quad Speed Mode)
o 24-Bit 8 times FIR Digital Filter
o On chip SCF
o Digital de-emphasis for 32k, 44.1k and 48kHz sampling
o Soft mute
o Digital Attenuator (256 steps)
o I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I
o Master clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode)
o THD+N: -94dB
o Dynamic Range: 112dB
o High Tolerance to Clock Jitter
o Power supply: 4.75 to 5.25V
o Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
2
S
DAC
MCLK
VDD
CSN
CCLK
CDTI
LRCK
BICK
SDTI
MS0034-E-002000/7
µP
Interface
Audio
Data
Interface
PDN
De-emphasis
Control
8X
Interpolator
8X
Interpolator
- 1 -
Clock
Divider
DS
Modulator
DS
Modulator
SCF
SCF
VSS
DZFL
DZFR
AOUTL+
AOUTL-
AOUTR+
AOUTR-
ASAHI KASEI[AK4382]
n Ordering Guide
AK4382VT-40 ~ +85°C16pin TSSOP (0.65mm pitch)
AKD4382Evaluation Board for AK4382
nPin Layout
MCLK
BICK
SDTI
LRCK
PDN
CSN
CCLK
CDTI
1
2
3
4
5
6
7
8
Top
View
PIN/FUNCTION
No.Pin NameI/OFunction
1MCLKIMaster Clock Input Pin
An external TTL clock should be input on this pin.
2BICKIAudio Serial Data Clock Pin
3SDTIIAudio Serial Data Input Pin
4LRCKIL/R Clock Pin
5PDNIPower-Down Mode Pin
When at “L”, the AK4382 is in the power-down mode and is held in reset.
The AK4382 should always be reset upon power-up.
6CSNIChip Select Pin
7CCLKIControl Data Input Pin
8CDTIIControl Data Input Pin in serial mode
9AOUTR-ORch Negative Analog Output Pin
10AOUTR+ORch Positive Analog Output Pin
11AOUTL-OLch Negative Analog Output Pin
12AOUTL+OLch Positive Analog Output P in
13VSS-Ground Pin
14VDD-Power Supply Pin
15DZFRORch Data Zero Input Detect Pin
16DZFLOLch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
16
15
14
13
12
11
10
DZFL
DZFR
VDD
VSS
AOUTL+
AOUTL-
AOUTR+
9
AOUTR-
MS0034-E-002000/7
- 2 -
ASAHI KASEI[AK4382]
ABSOLUTE MAXI MUM RATINGS
(VSS=0V; Note 1)
ParameterSymbolminmaxUnits
Power SupplyVDD-0.36.0V
Input Current (any pins except for supplies)IINInput VoltageVIND-0.3VDD+0.3V
Ambient Operating TemperatureTa-4085
Storage TemperatureTstg-65150
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
±10
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
ParameterSymbolmintypmaxUnits
Power SupplyVDD4.755.05.25V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0034-E-002000/7
- 3 -
ASAHI KASEI[AK4382]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ~ 20kHz; R
dB
Dynamic Range (-60dBFS with A-weighted) (Note 4)102112dB
S/N (A-weighted) (Note 5)102112dB
Interchannel Isolation (1kHz)90110dB
Interchannel Gain Mismatch0.20.5dB
DC Accuracy
Gain Drift100Output Voltage (Note 6)
±2.55±2.75±2.95
Load Resistance (Note 7)2
ppm/°C
Vpp
kW
Power Supplies
Power Supply Current (VDD)
Normal Operation (PDN = “H”, fs£96kHz)
Normal Operation (PDN = “H”, fs=192kHz)
Power-Down Mode (PDN = “L”) (Note 8)
20
25
10
34
42
100
mA
mA
µA
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5.
7. For AC-load. 4kW for DC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
PB0
FR
FR
FR
-18.2
-
-
-
+0/-5
+0/-4
+0/-5
8.1
kHz
-
-
-
-
kHz
dB
dB
dB
DC CHARACTERISTICS
(Ta=25°C; VDD=4.5 ~ 5.5V)
ParameterSymbolmintypmaxUnits
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage (Iout=80µA)
Input Leakage CurrentIin--
MS0034-E-002000/7
VIH
VIL
VOH
VOL
- 5 -
2.2
-
VDD-0.4
-
-
-
--
-
0.8
0.4
± 10
V
V
V
V
µA
ASAHI KASEI[AK4382]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.5 ~ 5.5V; CL=20pF)
ParameterSymbolmintypmaxUnits
Master Clock Frequency
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK Edge (Note 12)
LRCK Edge to BICK rising (Note 12)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “¯” to CCLK “”
CCLK “” to CSN “”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
Reset Timing
PDN Pulse Width (Note 13)
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.