PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
This set employs laser. Therefore, be sure to follow carefully the
instructions below when servicing.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT
WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO
CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE
FROM A DISTANCE OF MORE THAN 30cm FROM THE
SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL
PICK-UP BLOCK.
Caution: Invisible laser radiation when
open and interlocks defeated avoid exposure to beam.
Advarsel:Usynling laserståling ved åbning,
når sikkerhedsafbrydere er ude af funktion.
Undgå udsættelse for stråling.
VAROITUS!
Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainitulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylittävälle näkymättömälle lasersäteilylle.
VARNING!
Om apparaten används på annat sätt än vad som specificeras i
denna bruksanvising, kan användaren utsättas för osynling
laserstrålning, som överskrider gränsen för laserklass 1.
CAUTION
Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous
radiation exposure.
ATTENTION
L'utilisation de commandes, réglages ou procédures autres que
ceux spécifiés peut entraîner une dangereuse exposition aux
radiations.
ADVARSEL!
Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude
af funktion. Undgå udsættelse for stråling.
This Compact Disc player is classified as a CLASS 1 LASER
product.
The CLASS 1 LASER PRODUCT label is located on the rear
exterior.
CLASS 1
KLASSE 1
LUOKAN 1
KLASS 1
LASER PRODUCT
LASER PRODUKT
LASER LAITE
LASER APPARAT
-2-
Page 3
Precaution to replace Optical block
(SF-P200)
Body or clothes electrostatic potential could ruin
laser diode in the optical block. Be sure ground
body and workbench, and use care the clothes
do not touch the diode.
1) After the connection, remove solder shown in
the right figure.
:SOLDER
10 9
PICK UP ASSY
116
SF-P200
-3-
Page 4
SPECIFICATIONS
Design and specifications are subject to change without notice.
C117 87-010-196-080 CHIP CAPACITOR,0.1-25
C201 87-A10-505-040 CAP,E 220-6.3 105 SF
C202 87-010-175-080 CAP 560P
C204 87-010-213-080 C-CAP,S 0.015-50 B
C205 87-010-213-080 C-CAP,S 0.015-50 B
C206 87-A10-826-080 C-CAP,S 1-10 K B
C207 87-A10-826-080 C-CAP,S 1-10 K B
C208 87-010-177-080 C-CAP,S 820P-50 SL
C209 87-010-213-080 C-CAP,S 0.015-50 B
C210 87-010-213-080 C-CAP,S 0.015-50 B
C212 87-A10-826-080 C-CAP,S 1-10 K B
C301 87-016-557-040 CAP,E 100-6.3 SF
C302 87-010-502-040 CAP ELECT GAS 100/4
C303 87-016-557-040 CAP,E 100-6.3 SF
C304 87-010-502-040 CAP ELECT GAS 100/4
C313 87-A10-826-080 C-CAP,S 1-10 K B
C314 87-A10-201-080 C-CAP,S0.33-16 KB
C351 87-016-557-040 CAP,E 100-6.3 SF
C352 87-010-503-040 CAP,E 220-4 GAS
C353 87-A10-826-080 C-CAP,S 1-10 K B
C359 87-A10-369-080 C-CAP,S 0.47-16 K B
C360 87-016-669-080 C-CAP,S 0.1-25 K B
C361 87-010-322-080 C-CAP,S 100P-50 CH
C362 87-016-669-080 C-CAP,S 0.1-25 K B
C363 87-010-197-080 CAP, CHIP 0.01 DM
C364 87-016-369-080 C-CAP,S 0.033-25 B K
C365 87-010-322-080 C-CAP,S 100P-50 CH
C367 87-010-175-080 CAP 560P
C368 87-010-196-080 CHIP CAPACITOR,0.1-25
C701 87-010-501-040 E/CAP GAS 47-4
C702 87-010-495-040 CAP,E 2.2-50 GAS
C703 87-010-498-040 CAP,E 10-16 GAS
C704 87-010-503-040 CAP,E 220-4 GAS
C705 87-010-503-040 CAP,E 220-4 GAS
C706 87-010-498-040 CAP,E 10-16 GAS
C707 87-010-501-040 E/CAP GAS 47-4
C708 87-A10-826-080 C-CAP,S 1-10 K B
C709 87-A10-826-080 C-CAP,S 1-10 K B
C710 87-012-155-080 C-CAP 180P-50CH
C711 87-012-155-080 C-CAP 180P-50CH
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
CHIP RESISTOR PART CODE
Chip Resistor Part Coding
88
A
Resistor Code
Chip resistor
WattageTypeTolerance
1/16W10055%CJ
1/16W
1/10W
1/8W
1608
2125
3216
5%
5%
5%
Symbol
Figure
Value of resistor
CJ
CJ
CJ
Form
L
W
Dimensions (mm)
LW t
1.00.50.35104
t
1.60.80.45
21.25 0.45
1.6
0.55
3.2
Resistor Code
108
118
128
: A
: A
-6-
Page 7
TRANSISTOR ILLUSTRATION-1/1
C
B
E
2SA1037
2SC2412
CPH3106
DTC114TK
DTC123JK
BCE
2SB1132
2SD1664
D
G
S
2SK2980
-7-
Page 8
FL (AHC-7) GRID ASSIGNMENT/ANODE CONNECTION-1/1
GRID ASSIGNMENT
ANODE CONNECTION
-8-
Page 9
WIRING-1/1
101112131415161718192021222324
1234567892526272829303132
A
B
C
D
SF-P200
E
F
G
H
I
J
K
L
M
-9-
N
O
P
Q
R
S
T
U
Page 10
SCHEMATIC DIAGRAM-1/1
Z
-10-
Page 11
TEST MODE-1/3
IC101
IC351
IC701
IC201
IC801
IC301
27
Q305
RF
31
VC
TEST MODE SHORT LAND
-11-
Page 12
TEST MODE-2/3
The servo circuit of this model has been designed to be free of adjustments and controlled within the IC. Therefore, adjustments and disk judgement
are performed automatically every time the TOC is read out. The adjustment status of each servo inside the IC can be monitored in this test mode.
1. Startup procedure
1) Short the test land.
2) Insert the AC plug.
3) Press the STOP button. (The test mode starts.)
Note 1) The test mode is canceled by disconnecting the AC plug.
Note 2) The OPEN/CLOSE switch cannot be operated during the test mode.
2. Checking the RF level
Test point: RF & VC (Vref)
Test disk: TCD-782
Play back the disk and confirm that the RF waveform is in the following state:
0.8Vp-p or more
VOLT/DIV:200mV
TIME/DIV:0.5us
3. Checking each servo
The adjustment values of each servo can be checked by pressing the MODE button repeatedly during playback. The switching
procedure is as follows.
Check mode OFF™Vref offset (RO)™focus offset (FO)™tracking offset (TO)™tracking balance (TB)™tracking gain (TG) ™
focus gain (FG)™focus bias (FB)™check mode OFF
Example: Tracking offset (TO)Adjustment value™F5
RNDMRESUME
1
DSL
Tracking offset
* Adjustment values are indicated in hexadecimal.
When displaying each mode on the LCD and pressing the PLAY button in the STOP status, the center value is displayed on the LCD.
After the disk starts rotating, the adjustment value that was set during automatic adjustment is displayed. The display range of the
center values and adjustment values of each mode are as follows. There are 256 steps for displaying the values of all modes.
Center value
1) Vref offset (RO)
2) Focus offset (FO)
3) Tracking offset (TO)
4) Tracking balance (TB)
5) Tracking gain (TG)
6) Focus gain (FG)
7) Focus bias (FB)
Adjustment value
Center value
00
00
00
80
40
40
00
Display range
80-7F
80-7F
80-7F
00-FF
00-FF
00-FF
80-7F
-12-
Page 13
TEST MODE-3/3
4. Amount of change of jitter
The amount of change of jitter is displayed in the focus bias check mode. The displayed value has 256 steps from 00 to FF.
Internal VCD power supply pin. (2000pF or more path controller to be inserted at a point nearer
to the pin between this pin and GND)
VCD frequency range adjustment resistor connection pin. (pull up)
I
Mirror detection signal input pin.
I
SLCO output current adjustment resistor connection pin. (pull up)
I
Control outout.
O
EFM signal input pin.
I
Jitter detection monitor pin.
O
Jitter detection adjustment pin.
O
BH signal input pin. A/D input. (Must be connected to OV when unused)
I
PH signal or RFENV signal input pin. A/D input.
I
FE signal input pin. A/D input.
I
TE signal input pin. A/D input.
I
VREF input pin. A/D input.
I
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
ADAVDD
ADAVSS
PHREF
BHREF
TBLO
TDO
FDO
SPDO
SLDO
DVREF/FG
LASER
CONT1
CONT2
CONT3
CONT4
CONT5
—
—
O
O
O
O
O
O
O
I/O
O
I/O
I/O
I/O
I/O
I/O
Servo A/D, D/A power supply pin. (2000pF or more path controller to be inserted at a point
nearer to the pin between this pin and GND)
Servo A/D, D/A ground pin.
PH reference output pin. D/A output. (Not connected)
BH reference output pin. D/A output. (Not connected)
Tracking balance output pin. D/A output.
Tracking control output pin. D/A output.
Focus control output pin. D/A output.
Spindle control output pin. D/A output.
Thread control output pin. D/A output.
Output driver VREF output pin. Input FG signal input pin. (Must be connected to OV when
unused) (Not connected)
Laser ON/OFF control pin.
General-purpose input/output pin 1. (Not connected)
General-purpose input/output pin 2. (Not connected)
General-purpose input/output pin 3. (Not connected)
General-purpose input/output pin 4.
General-purpose input/output pin 5.
34
35
36
PCK
C2F
VDD
—
EFM data playback clock monitor pin. Average 4.3218MHz when the phase is locked.
O
(Not connected)
C2 flag output pin. (Not connected)
O
Digital power supply pin. (2000pF or more path controller to be inserted at a point nearer to the
pin between this pin and GND)
-16-
Page 17
IC DESCRIPTION-1/3 (LC78641NE-D)-2/3
Pin No.Pin NameI/ODescription
37
DOUT
Digital OUT output pin. (EIAJ format) (Not connected)
O
38
39
40
41
42
43
44
45
46
47
48
49
50
FSX
EFLG
TEST
EMPH
MUTEL
MUTER
LVDD
LCHO
LVSS
RVSS
RCHO
RVDD
XVDD
O
O
I/O
O
O
—
O
—
—
O
—
—
Output pin for the 7.35kHz synchronization signal divided from the crystal osillator.
(Not connected)
(Not connected)
C1 C2 error correction monitor pin. Test input pin. Must be connected to OV.
I
Emphasis pin. Which becomes an input pin after reset and can becontrolled externally.
This becomes an emphasis monitor pin under control by command. (Not connected)
L channnel mute output pin.
R channel mute output pin.
L channel power supply pin. (2000pF or more path controller to be inserted at a point
nearer to the pin between this pin and GND)
L channel output pin.
L channel ground pin, Must be connected to 0V.
R channel ground pin, Must be connected to 0V.
R channel output pin.
R channel power supply pin. (2000pF or more path controller to be inserted at a point
nearer to the pin between this pin and GND)
Crystal oscillator power supply pin. (2000pF or more path controller to be inserted at a
point nearer to the pin between this pin and GND)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
XIN
XOUT
XVSS
ASLRCK
ASDACK
ASDFIN
LRSY
DATACK
DATA
16M
SFSY
SBSY
PW
SBCK
CE
CL
I
Connections for a 16.9344MHz crystal oscillator pin.
O
Crystal oscillator ground pin. Must be connected to 0V.
—
L/R clock input pin. (Must be connected to 0V when unused)
I
Bit clock input pin. (Must be connected to 0V when unused)
I
L/R channel data input pin. (Must be connected to 0V when unused)
I
L/R clock output pin.
O
Bit clock output pin. (Not connected)
O
L/R channel data output pin. (Not connected)
O
16.9344MHz output pin. (Not connected)
O
Subcode frame synchronization signal output pin. This signal falls when the subcode is
O
in the standby state. (Not connected)
Subcode clock synchronization signal output pin. (Not connected)
O
Subcode P, Q, R, S, T, U and W output pin. (Not connected)
O
Subcode readout clock input pin.
I
Chip enable signal input pin.
I
Data transfer clock input pin.
I
67
68
69
70
71
DI
DO
INT
WRQ
RES
Data input pin.
I
Data output pin.
O
Interruption signal output pin. (Not connected)
O
Interruption signal output pin.
O
Reset input pin. This pin must be set low briefly after power is first applied.
I
-17-
Page 18
IC DESCRIPTION-1/3 (LC78641NE-D)-3/3
Pin No.Pin NameI/ODescription
72
DRF
Focus ON detect pin.
O
73
74
75
76
77
78
79
80
VDD5V
VSS
CONT6
CONT7
V/P
FSEQ
DFECT
EFMO
—
—
I/O
I/O
O
O
I/O
O
Microprocessor interface power supply. (2000pF or more path controller to be inserted
at a point nearer to the pin between this pin and GND)
Digital ground pin. Must be connected to 0V.
General-purpose input/output pin 6. (Not connected)
General-pirpose input/output pin 7. (Not connected)
Rough servo/phase control automatic switching monitor output pin. “H” for rough
servo and “L” for phase servo. (Not connected)
Synchronization signal detection output pin. Outputs a high level when the
synchronization signal detected from the EFM signal and the internally generated
synchronization signal agree. (Not connected)
Defect pin. Which becomes an input pin after reset and can be controlled externally.
This becomes the defect monitor pin under control by command. (Not connected)
EFM signal output pin. (Not connected)
-18-
Page 19
IC DESCRIPTION-2/3 (µPD789406AGC-014)-1/2
Pin No.Pin NameI/ODescription
1
VDD1
—
Positive polarity power supply (except for port section).
2
3-5
6
7-10
11-26
27-30
31
32
33
34-37
38
39
40
41
42
43
44
BIAS
VLC0-VLC2
VSS1
COM0-COM3
S0-S15
P93-P90
P87
P86
P85
P84-P81
P80
AVDD
AVREF
ANI6/P66
ANI5/P65
ANI4/P64
ANI3/P63
—
—
—
—
—
Feeding the LCD drive power supply voltage.
LCD drive power supply voltage.
Ground potential (except for port section).
Common signal output from LCD controller/driver.
Signal name: MUTLR. Zero data detection. MUTE at CDH or more.
I
Connected to Ground.
I
A/D comparator ground potential.
Signal name: DRF. Focus ON detection signal.
I
Not connected.
O
Signal name: WRQ. Interrupt signal from DSP.
I
Signal name: DO. Serial data reception from DSP.
I
Signal name: BEEP. Square wave output for BEEP sound.
O
Signal name: DI. Data output to DSP.
O
Signal name: CE. Chip enable output to DSP.
O
Signal name: CL. Serial clock output to DSP.
O
Signal name: K-STOP. H: When STOP button is pressed.
I
Signal name: K-PLAY. H: When PLAY button is pressed.
I
Signal name: ACDECT. H: AC adapter is detected.
I
Not connected.
O
Signal name: SPCON. H: Spindle stop.
O
62
63
64
65
66
67
P02
P01
P00
P47
P46
_____________
RESET
Signal name: SLCON. H: Sled stop.
O
Signal name: LSW. L: Sled inner circumference limit.
I
Signal name: APOFF. L: DC-DC CONV OFF.
O
Not connected.
O
Signal name: XRST. L: DSP reset.
O
System reset input.
I
-19-
Page 20
IC DESCRIPTION-2/3 (µPD789406AGC-014)-2/2
Pin No.Pin NameI/ODescription
68
69
X2
X1
—
Terminal to connect external crystal for main system clock oscillation.
I
70
71
72
73
74
75
76
77
78
79, 80
VSS0
VDD0
XT2
XT1
IC/VPP
P45
P44
P43
P42
P41, P40
—
—
—
—
Ground potential of port section.
Positive polarity power supply for port section.
Not connected.
I
Terminal to connect external crystal for sub system clock oscillation. (Connected to Ground)
This pin is internally connected. Connect this pin directly to Vss0 or Vss1.
O
Signal name: SDBY. H: Output amplifier operates.
O
Signal name: MUTE. H: MUTE ON (Output amplifier).
O
Signal name: DSL1. L: DSL ON (Step 1).
O
Signal name: DSL2. H: DSL ON (Step 2) (When DSL1 is H).
O
Not connected.
-20-
Page 21
IC DESCRIPTION-3/3 (LA9253M)-1/1
Pin No.Pin NameI/ODescription
1
FIN1
I
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
FIN2
TIN1
TIN2
REF1
VREF
LDS
LDD
GND
LDOF
ODRV
AGON
EFBL
TESO
TESI
TES
HFL
TE
—
I
Pick-up signal input.
I
I
Pin designed for reference voltage.
I
Reference voltage output.
O
APC monitor voltage input.
I
APC output.
O
GND.
Laser OFF pin. (H: ON L: OFF)
I
Speed switch pin. (H: double L: normal speed)
I
AGC ON pin. (H: ON L: OFF)
I
FE balance adjustment pin.
I
TE signal output for TES. (Not connected)
O
TE input for TES formation. (Not connected)
I
TES output. (Not connected)
O
HFL signal output.
O
TE signal output.
O
19
20
21
22
23
24
25
26
27
28
29
30
TE-
FE
FE-
RFEV
N/C
BH
PH
N/C
RF
RF-
RFSW
VCC
—
—
—
Minus input for TE gain design.
I
FE signal output.
O
Minus input for FE gain design.
I
RF envelop signal output.
O
Pin N/C.
Capasitance connection pin for RF bottom clamp.
I
Capasitance connection pin for RF gain design.
I
Pin N/C.
RF signal output.
O
Minus input for RF signal gain design.
I
Switch for equalizer design when RF has double speed.
I
Power supply.
-21-
Page 22
MECHANICAL EXPLODED VIEW-1/1
8
8
1
LCD
9
PWB
DA23L
8
10
B
12
11
2
3
4
5
7
13
6
a
A
15
14
a
-22-
Page 23
MECHANICAL PARTS LIST-1/1
REF. NOPART NO.KANRIDESCRIPTION
1 8A-HC7-007-010 WINDOW,CD
2 8A-HC7-138-010 WINDOW,DISPLAY 319
3 8A-HC7-017-110 LID ASSY,CD
4 85-HC6-205-110 SHAFT,LID(300) HK
5 8A-HC7-204-010 SPR-T,OPEN